mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a2b2200ff8
its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
435 lines
16 KiB
TableGen
435 lines
16 KiB
TableGen
//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MIPS register file
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//===----------------------------------------------------------------------===//
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let Namespace = "Mips" in {
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def sub_fpeven : SubRegIndex;
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def sub_fpodd : SubRegIndex;
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def sub_32 : SubRegIndex;
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def sub_lo : SubRegIndex;
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def sub_hi : SubRegIndex;
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def sub_dsp16_19 : SubRegIndex;
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def sub_dsp20 : SubRegIndex;
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def sub_dsp21 : SubRegIndex;
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def sub_dsp22 : SubRegIndex;
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def sub_dsp23 : SubRegIndex;
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}
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class Unallocatable {
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bit isAllocatable = 0;
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}
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// We have banks of 32 registers each.
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class MipsReg<bits<16> Enc, string n> : Register<n> {
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let HWEncoding = Enc;
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let Namespace = "Mips";
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}
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class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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let HWEncoding = Enc;
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let Namespace = "Mips";
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}
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// Mips CPU Registers
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class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
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// Mips 64-bit CPU Registers
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class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_32];
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}
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// Mips 32-bit FPU Registers
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class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
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// Mips 64-bit (aliased) FPU Registers
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class AFPR<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_fpeven, sub_fpodd];
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let CoveredBySubRegs = 1;
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}
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class AFPR64<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_32];
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}
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// Accumulator Registers
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class ACC<bits<16> Enc, string n, list<Register> subregs>
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: MipsRegWithSubRegs<Enc, n, subregs> {
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let SubRegIndices = [sub_lo, sub_hi];
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let CoveredBySubRegs = 1;
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}
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// Mips Hardware Registers
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class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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let Namespace = "Mips" in {
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// General Purpose Registers
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def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
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def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>;
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def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
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def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
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def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
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def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
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def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
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def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
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def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
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def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
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def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
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def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
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def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
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def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
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def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
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def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
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def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
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def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
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def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
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def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
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def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
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def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
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def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
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def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
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def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
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def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
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def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
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def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
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def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
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def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
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def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
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// General Purpose 64-bit Registers
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def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
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def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>;
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def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
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def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
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def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
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def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
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def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
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def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
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def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
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def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
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def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
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def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
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def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
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def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
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def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
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def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
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def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
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def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
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def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
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def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
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def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
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def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
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def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
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def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
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def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
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def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
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def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
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def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
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def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
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def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
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def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
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def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
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/// Mips Single point precision FPU Registers
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def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
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def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>;
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def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>;
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def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>;
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def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>;
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def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>;
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def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>;
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def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>;
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def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>;
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def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>;
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def F10 : FPR<10, "f10">, DwarfRegNum<[42]>;
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def F11 : FPR<11, "f11">, DwarfRegNum<[43]>;
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def F12 : FPR<12, "f12">, DwarfRegNum<[44]>;
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def F13 : FPR<13, "f13">, DwarfRegNum<[45]>;
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def F14 : FPR<14, "f14">, DwarfRegNum<[46]>;
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def F15 : FPR<15, "f15">, DwarfRegNum<[47]>;
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def F16 : FPR<16, "f16">, DwarfRegNum<[48]>;
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def F17 : FPR<17, "f17">, DwarfRegNum<[49]>;
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def F18 : FPR<18, "f18">, DwarfRegNum<[50]>;
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def F19 : FPR<19, "f19">, DwarfRegNum<[51]>;
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def F20 : FPR<20, "f20">, DwarfRegNum<[52]>;
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def F21 : FPR<21, "f21">, DwarfRegNum<[53]>;
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def F22 : FPR<22, "f22">, DwarfRegNum<[54]>;
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def F23 : FPR<23, "f23">, DwarfRegNum<[55]>;
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def F24 : FPR<24, "f24">, DwarfRegNum<[56]>;
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def F25 : FPR<25, "f25">, DwarfRegNum<[57]>;
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def F26 : FPR<26, "f26">, DwarfRegNum<[58]>;
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def F27 : FPR<27, "f27">, DwarfRegNum<[59]>;
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def F28 : FPR<28, "f28">, DwarfRegNum<[60]>;
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def F29 : FPR<29, "f29">, DwarfRegNum<[61]>;
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def F30 : FPR<30, "f30">, DwarfRegNum<[62]>;
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def F31 : FPR<31, "f31">, DwarfRegNum<[63]>;
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/// Mips Double point precision FPU Registers (aliased
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/// with the single precision to hold 64 bit values)
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def D0 : AFPR< 0, "f0", [F0, F1]>;
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def D1 : AFPR< 2, "f2", [F2, F3]>;
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def D2 : AFPR< 4, "f4", [F4, F5]>;
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def D3 : AFPR< 6, "f6", [F6, F7]>;
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def D4 : AFPR< 8, "f8", [F8, F9]>;
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def D5 : AFPR<10, "f10", [F10, F11]>;
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def D6 : AFPR<12, "f12", [F12, F13]>;
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def D7 : AFPR<14, "f14", [F14, F15]>;
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def D8 : AFPR<16, "f16", [F16, F17]>;
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def D9 : AFPR<18, "f18", [F18, F19]>;
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def D10 : AFPR<20, "f20", [F20, F21]>;
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def D11 : AFPR<22, "f22", [F22, F23]>;
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def D12 : AFPR<24, "f24", [F24, F25]>;
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def D13 : AFPR<26, "f26", [F26, F27]>;
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def D14 : AFPR<28, "f28", [F28, F29]>;
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def D15 : AFPR<30, "f30", [F30, F31]>;
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/// Mips Double point precision FPU Registers in MFP64 mode.
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def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>;
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def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>;
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def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>;
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def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>;
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def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>;
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def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>;
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def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>;
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def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>;
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def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>;
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def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>;
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def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>;
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def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>;
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def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>;
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def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>;
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def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>;
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def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>;
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def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>;
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def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>;
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def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>;
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def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>;
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def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>;
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def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>;
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def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>;
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def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>;
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def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>;
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def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>;
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def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>;
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def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>;
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def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>;
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def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>;
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def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>;
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def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>;
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// Hi/Lo registers
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def HI : Register<"ac0">, DwarfRegNum<[64]>;
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def HI1 : Register<"ac1">, DwarfRegNum<[176]>;
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def HI2 : Register<"ac2">, DwarfRegNum<[178]>;
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def HI3 : Register<"ac3">, DwarfRegNum<[180]>;
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def LO : Register<"ac0">, DwarfRegNum<[65]>;
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def LO1 : Register<"ac1">, DwarfRegNum<[177]>;
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def LO2 : Register<"ac2">, DwarfRegNum<[179]>;
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def LO3 : Register<"ac3">, DwarfRegNum<[181]>;
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let SubRegIndices = [sub_32] in {
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def HI64 : RegisterWithSubRegs<"hi", [HI]>;
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def LO64 : RegisterWithSubRegs<"lo", [LO]>;
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}
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// Status flags register
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def FCR31 : Register<"31">;
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// fcc0 register
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def FCC0 : MipsReg<0, "fcc0">;
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// PC register
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def PC : Register<"pc">;
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// Hardware register $29
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def HWR29 : MipsReg<29, "29">;
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def HWR29_64 : MipsReg<29, "29">;
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// Accum registers
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def AC0 : ACC<0, "ac0", [LO, HI]>;
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def AC1 : ACC<1, "ac1", [LO1, HI1]>;
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def AC2 : ACC<2, "ac2", [LO2, HI2]>;
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def AC3 : ACC<3, "ac3", [LO3, HI3]>;
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def AC0_64 : ACC<0, "ac0", [LO64, HI64]>;
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// DSP-ASE control register fields.
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def DSPPos : Register<"">;
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def DSPSCount : Register<"">;
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def DSPCarry : Register<"">;
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def DSPEFI : Register<"">;
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def DSPOutFlag16_19 : Register<"">;
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def DSPOutFlag20 : Register<"">;
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def DSPOutFlag21 : Register<"">;
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def DSPOutFlag22 : Register<"">;
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def DSPOutFlag23 : Register<"">;
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def DSPCCond : Register<"">;
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let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
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sub_dsp23] in
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def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
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DSPOutFlag21, DSPOutFlag22,
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DSPOutFlag23]>;
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}
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//===----------------------------------------------------------------------===//
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// Register Classes
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//===----------------------------------------------------------------------===//
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class CPURegsClass<list<ValueType> regTypes> :
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RegisterClass<"Mips", regTypes, 32, (add
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// Reserved
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ZERO, AT,
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// Return Values and Arguments
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V0, V1, A0, A1, A2, A3,
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// Not preserved across procedure calls
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T0, T1, T2, T3, T4, T5, T6, T7,
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// Callee save
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S0, S1, S2, S3, S4, S5, S6, S7,
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// Not preserved across procedure calls
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T8, T9,
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// Reserved
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K0, K1, GP, SP, FP, RA)>;
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def CPURegs : CPURegsClass<[i32]>;
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def DSPRegs : CPURegsClass<[v4i8, v2i16]>;
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def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
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// Reserved
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ZERO_64, AT_64,
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// Return Values and Arguments
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V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
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// Not preserved across procedure calls
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T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
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// Callee save
|
|
S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
|
|
// Not preserved across procedure calls
|
|
T8_64, T9_64,
|
|
// Reserved
|
|
K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
|
|
|
|
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
|
|
// Return Values and Arguments
|
|
V0, V1, A0, A1, A2, A3,
|
|
// Callee save
|
|
S0, S1)>;
|
|
|
|
def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
|
|
|
|
def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
|
|
|
|
// 64bit fp:
|
|
// * FGR64 - 32 64-bit registers
|
|
// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
|
|
//
|
|
// 32bit fp:
|
|
// * FGR32 - 16 32-bit even registers
|
|
// * FGR32 - 32 32-bit registers (single float only mode)
|
|
def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
|
|
|
|
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
|
|
// Return Values and Arguments
|
|
D0, D1,
|
|
// Not preserved across procedure calls
|
|
D2, D3, D4, D5,
|
|
// Return Values and Arguments
|
|
D6, D7,
|
|
// Not preserved across procedure calls
|
|
D8, D9,
|
|
// Callee save
|
|
D10, D11, D12, D13, D14, D15)>;
|
|
|
|
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
|
|
|
|
// Condition Register for floating point operations
|
|
def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
|
|
|
|
// Hi/Lo Registers
|
|
def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;
|
|
def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>;
|
|
def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>;
|
|
def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>;
|
|
def LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>;
|
|
def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>;
|
|
|
|
// Hardware registers
|
|
def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
|
|
def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable;
|
|
|
|
// Accumulator Registers
|
|
def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
|
|
let Size = 64;
|
|
}
|
|
|
|
def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
|
|
let Size = 128;
|
|
}
|
|
|
|
def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
|
|
let Size = 64;
|
|
}
|
|
|
|
def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
|
|
|
|
// Register Operands.
|
|
def CPURegsAsmOperand : AsmOperandClass {
|
|
let Name = "CPURegsAsm";
|
|
let ParserMethod = "parseCPURegs";
|
|
}
|
|
|
|
def CPU64RegsAsmOperand : AsmOperandClass {
|
|
let Name = "CPU64RegsAsm";
|
|
let ParserMethod = "parseCPU64Regs";
|
|
}
|
|
|
|
def CCRAsmOperand : AsmOperandClass {
|
|
let Name = "CCRAsm";
|
|
let ParserMethod = "parseCCRRegs";
|
|
}
|
|
|
|
def CPURegsOpnd : RegisterOperand<CPURegs, "printCPURegs"> {
|
|
let ParserMatchClass = CPURegsAsmOperand;
|
|
}
|
|
|
|
def CPU64RegsOpnd : RegisterOperand<CPU64Regs, "printCPURegs"> {
|
|
let ParserMatchClass = CPU64RegsAsmOperand;
|
|
}
|
|
|
|
def CCROpnd : RegisterOperand<CCR, "printCPURegs"> {
|
|
let ParserMatchClass = CCRAsmOperand;
|
|
}
|
|
|
|
def HWRegsAsmOperand : AsmOperandClass {
|
|
let Name = "HWRegsAsm";
|
|
let ParserMethod = "parseHWRegs";
|
|
}
|
|
|
|
def HW64RegsAsmOperand : AsmOperandClass {
|
|
let Name = "HW64RegsAsm";
|
|
let ParserMethod = "parseHW64Regs";
|
|
}
|
|
|
|
def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> {
|
|
let ParserMatchClass = HWRegsAsmOperand;
|
|
}
|
|
|
|
def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> {
|
|
let ParserMatchClass = HW64RegsAsmOperand;
|
|
}
|