Daniel Sanders 6ff1ef9931 [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) ... This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-30 14:45:14 +00:00
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llvm	[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)	2013-10-30 14:45:14 +00:00
llvm-c	llvm-c: Make LLVM{Get,Set}Alignment work on {Load,Store}Inst too	2013-10-29 09:02:02 +00:00