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f63be7d395
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
8.5 KiB
C++
225 lines
8.5 KiB
C++
//===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRUCTIONINFO_H
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#define X86INSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "X86RegisterInfo.h"
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namespace llvm {
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/// X86II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace X86II {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction types. These are the standard/most common forms for X86
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// instructions.
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//
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// PseudoFrm - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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Pseudo = 0,
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/// Raw - This form is for instructions that don't have any operands, so
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/// they are just a fixed opcode value, like 'leave'.
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RawFrm = 1,
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/// AddRegFrm - This form is used for instructions like 'push r32' that have
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/// their one register operand added to their opcode.
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AddRegFrm = 2,
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/// MRMDestReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is a register.
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///
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MRMDestReg = 3,
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/// MRMDestMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a destination, which in this case is memory.
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///
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MRMDestMem = 4,
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/// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is a register.
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///
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MRMSrcReg = 5,
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/// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
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/// to specify a source, which in this case is memory.
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///
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MRMSrcMem = 6,
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/// MRM[0-7][rm] - These forms are used to represent instructions that use
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/// a Mod/RM byte, and use the middle field to hold extended opcode
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/// information. In the intel manual these are represented as /0, /1, ...
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///
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// First, instructions that operate on a register r/m operand...
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MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
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MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
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// Next, instructions that operate on a memory r/m operand...
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MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
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MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
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FormMask = 31,
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//===------------------------------------------------------------------===//
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// Actual flags...
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data.
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OpSize = 1 << 5,
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// Op0Mask - There are several prefix bytes that are used to form two byte
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// opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
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// used to obtain the setting of this field. If no bits in this field is
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// set, there is no prefix byte for obtaining a multibyte opcode.
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//
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Op0Shift = 6,
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Op0Mask = 0xF << Op0Shift,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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TB = 1 << Op0Shift,
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// REP - The 0xF3 prefix byte indicating repetition of the following
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// instruction.
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REP = 2 << Op0Shift,
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// D8-DF - These escape opcodes are used by the floating point unit. These
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// values must remain sequential.
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D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
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DA = 5 << Op0Shift, DB = 6 << Op0Shift,
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DC = 7 << Op0Shift, DD = 8 << Op0Shift,
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DE = 9 << Op0Shift, DF = 10 << Op0Shift,
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// XS, XD - These prefix codes are for single and double precision scalar
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// floating point operations performed in the SSE registers.
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XD = 11 << Op0Shift, XS = 12 << Op0Shift,
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//===------------------------------------------------------------------===//
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// This two-bit field describes the size of an immediate operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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ImmShift = 10,
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ImmMask = 7 << ImmShift,
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Imm8 = 1 << ImmShift,
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Imm16 = 2 << ImmShift,
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Imm32 = 3 << ImmShift,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeShift = 12,
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FPTypeMask = 7 << FPTypeShift,
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// NotFP - The default, set for instructions that do not use FP registers.
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NotFP = 0 << FPTypeShift,
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// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
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ZeroArgFP = 1 << FPTypeShift,
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// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
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OneArgFP = 2 << FPTypeShift,
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// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
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// result back to ST(0). For example, fcos, fsqrt, etc.
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//
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OneArgFPRW = 3 << FPTypeShift,
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// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
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// explicit argument, storing the result to either ST(0) or the implicit
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << FPTypeShift,
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// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
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// explicit argument, but have no destination. Example: fucom, fucomi, ...
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CompareFP = 5 << FPTypeShift,
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// CondMovFP - "2 operand" floating point conditional move instructions.
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CondMovFP = 6 << FPTypeShift,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 7 << FPTypeShift,
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// Bit 15 is unused.
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OpcodeShift = 16,
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OpcodeMask = 0xFF << OpcodeShift,
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// Bits 24 -> 31 are unused
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};
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}
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class X86InstrInfo : public TargetInstrInfo {
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const X86RegisterInfo RI;
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public:
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X86InstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const;
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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/// Insert a goto (unconditional branch) sequence to TMBB, at the
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/// end of MBB
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virtual void insertGoto(MachineBasicBlock& MBB,
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MachineBasicBlock& TMBB) const;
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/// Reverses the branch condition of the MachineInstr pointed by
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/// MI. The instruction is replaced and the new MI is returned.
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virtual MachineBasicBlock::iterator
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reverseBranchCondition(MachineBasicBlock::iterator MI) const;
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified opcode number.
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//
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unsigned char getBaseOpcodeFor(unsigned Opcode) const {
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return get(Opcode).TSFlags >> X86II::OpcodeShift;
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}
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};
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} // End llvm namespace
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#endif
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