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7032f922b1
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs) instruction form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1004 B
LLVM
46 lines
1004 B
LLVM
; RUN: llc < %s -march=arm | FileCheck %s
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define i64 @f0(i64 %A, i64 %B) {
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; CHECK: f0
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; CHECK: lsrs r3, r3, #1
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; CHECK-NEXT: rrx r2, r2
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbc r1, r1, r3
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%tmp = bitcast i64 %A to i64
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%tmp2 = lshr i64 %B, 1
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%tmp3 = sub i64 %tmp, %tmp2
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ret i64 %tmp3
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}
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define i32 @f1(i64 %x, i64 %y) {
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; CHECK: f1
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; CHECK: lsl{{.*}}r2
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%a = shl i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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define i32 @f2(i64 %x, i64 %y) {
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; CHECK: f2
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; CHECK: lsr{{.*}}r2
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: subs r2, r2, #32
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; CHECK-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-NEXT: movge r0, r1, asr r2
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%a = ashr i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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define i32 @f3(i64 %x, i64 %y) {
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; CHECK: f3
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; CHECK: lsr{{.*}}r2
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: subs r2, r2, #32
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; CHECK-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-NEXT: movge r0, r1, lsr r2
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%a = lshr i64 %x, %y
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%b = trunc i64 %a to i32
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ret i32 %b
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}
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