Krzysztof Parzyszek 703ff349ac [Hexagon] Generate MUX from conditional transfers when dot-new not possible ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242711 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-20 21:23:25 +00:00
..
AArch64	[AArch64] Change EON pattern to match more often.	2015-07-20 18:42:27 +00:00
AMDGPU	AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops	2015-07-20 14:28:41 +00:00
ARM	ARM: Enable MachineScheduler and disable PostRAScheduler for swift.	2015-07-17 23:18:30 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Generate MUX from conditional transfers when dot-new not possible	2015-07-20 21:23:25 +00:00
Inputs
Mips
MIR	MIR Serialization: Initial serialization of machine constant pools.	2015-07-20 20:51:18 +00:00
MSP430
NVPTX	Use inbounds GEPs for memcpy and memset lowering	2015-07-17 16:42:33 +00:00
PowerPC	Add missing test for r242296 (vec_sld)	2015-07-20 15:43:21 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: Add scheduling information for LDRLIT instructions to swift scheduling model	2015-07-17 23:18:26 +00:00
WebAssembly
WinEH
X86	[ImplicitNullChecks] Work with implicit defs.	2015-07-20 20:31:39 +00:00
XCore