mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-24 06:30:19 +00:00
8d30c23d26
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };
instead of this:
static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };
For operand information, which does not require dynamic (startup-time)
initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22931 91177308-0d34-0410-b5e6-96231b3b80d8
270 lines
9.5 KiB
C++
270 lines
9.5 KiB
C++
//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "InstrInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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using namespace llvm;
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// runEnums - Print out enum values for all of the instructions.
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void InstrInfoEmitter::runEnums(std::ostream &OS) {
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EmitSourceFileHeader("Target Instruction Enum Values", OS);
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OS << "namespace llvm {\n\n";
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CodeGenTarget Target;
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// We must emit the PHI opcode first...
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Record *InstrInfo = Target.getInstructionSet();
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std::string Namespace = Target.inst_begin()->second.Namespace;
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << " enum {\n";
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
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OS << " " << NumberedInstructions[i]->TheDef->getName()
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<< ", \t// " << i << "\n";
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}
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OS << " };\n";
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if (!Namespace.empty())
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OS << "}\n";
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OS << "} // End llvm namespace \n";
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}
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static std::vector<Record*> GetDefList(ListInit *LI, const std::string &Name) {
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std::vector<Record*> Result;
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for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
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if (DefInit *DI = dynamic_cast<DefInit*>(LI->getElement(i)))
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Result.push_back(DI->getDef());
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else
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throw "Illegal value in '" + Name + "' list!";
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return Result;
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}
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void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
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unsigned Num, std::ostream &OS) const {
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OS << "static const unsigned ImplicitList" << Num << "[] = { ";
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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OS << getQualifiedName(Uses[i]) << ", ";
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OS << "0 };\n";
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}
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static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<Record*> Result;
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if (Inst.hasVariableNumberOfOperands)
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return Result; // No info for variable operand instrs.
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for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
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if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass"))
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Result.push_back(Inst.OperandList[i].Rec);
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else {
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// This might be a multiple operand thing.
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// FIXME: Targets like X86 have registers in their multi-operand operands.
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for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j)
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Result.push_back(0);
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}
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}
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return Result;
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}
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// run - Emit the main instruction description records for the target...
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void InstrInfoEmitter::run(std::ostream &OS) {
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EmitSourceFileHeader("Target Instruction Descriptors", OS);
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OS << "namespace llvm {\n\n";
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CodeGenTarget Target;
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const std::string &TargetName = Target.getName();
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Record *InstrInfo = Target.getInstructionSet();
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Record *PHI = InstrInfo->getValueAsDef("PHIInst");
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// Emit empty implicit uses and defs lists
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OS << "static const unsigned EmptyImpList[] = { 0 };\n";
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// Keep track of all of the def lists we have emitted already.
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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std::map<ListInit*, unsigned> ListNumbers;
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unsigned ListNumber = 0;
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// Emit all of the instruction's implicit uses and defs.
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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Record *Inst = II->second.TheDef;
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ListInit *LI = Inst->getValueAsListInit("Uses");
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if (LI->getSize()) {
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std::vector<Record*> Uses = GetDefList(LI, Inst->getName());
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unsigned &IL = EmittedLists[Uses];
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if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
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ListNumbers[LI] = IL;
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}
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LI = Inst->getValueAsListInit("Defs");
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if (LI->getSize()) {
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std::vector<Record*> Uses = GetDefList(LI, Inst->getName());
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unsigned &IL = EmittedLists[Uses];
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if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
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ListNumbers[LI] = IL;
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}
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}
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std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
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unsigned OperandListNum = 0;
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OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
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// Emit all of the operand info records.
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OS << "\n";
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
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unsigned &N = OperandInfosEmitted[OperandInfo];
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if (N == 0) {
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N = ++OperandListNum;
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OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
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for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
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if (Record *RC = OperandInfo[i]) {
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OS << "{ &" << getQualifiedName(RC) << "RegClass }, ";
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} else {
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OS << "{ 0 }, ";
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}
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}
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OS << "};\n";
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}
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}
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// Emit all of the TargetInstrDescriptor records.
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//
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OS << "\nstatic const TargetInstrDescriptor " << TargetName
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<< "Insts[] = {\n";
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emitRecord(Target.getPHIInstruction(), 0, InstrInfo, ListNumbers,
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OperandInfosEmitted, OS);
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unsigned i = 0;
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II)
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if (II->second.TheDef != PHI)
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emitRecord(II->second, ++i, InstrInfo, ListNumbers,
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OperandInfosEmitted, OS);
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OS << "};\n";
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OS << "} // End llvm namespace \n";
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}
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void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<ListInit*, unsigned> &ListNumbers,
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std::map<std::vector<Record*>, unsigned> &OpInfo,
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std::ostream &OS) {
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int NumOperands;
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if (Inst.hasVariableNumberOfOperands)
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NumOperands = -1;
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else if (!Inst.OperandList.empty())
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// Each logical operand can be multiple MI operands.
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NumOperands = Inst.OperandList.back().MIOperandNo +
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Inst.OperandList.back().MINumOperands;
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else
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NumOperands = 0;
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OS << " { \"";
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if (Inst.Name.empty())
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OS << Inst.TheDef->getName();
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else
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OS << Inst.Name;
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OS << "\",\t" << NumOperands << ", -1, 0, false, 0, 0, 0, 0";
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// Emit all of the target indepedent flags...
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if (Inst.isReturn) OS << "|M_RET_FLAG";
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if (Inst.isBranch) OS << "|M_BRANCH_FLAG";
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if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
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if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
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if (Inst.isCall) OS << "|M_CALL_FLAG";
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if (Inst.isLoad) OS << "|M_LOAD_FLAG";
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if (Inst.isStore) OS << "|M_STORE_FLAG";
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if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
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if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
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if (Inst.isCommutable) OS << "|M_COMMUTABLE";
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if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
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OS << ", 0";
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// Emit all of the target-specific flags...
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ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
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ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
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if (LI->getSize() != Shift->getSize())
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throw "Lengths of " + InstrInfo->getName() +
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":(TargetInfoFields, TargetInfoPositions) must be equal!";
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for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
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emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
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dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
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OS << ", ";
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// Emit the implicit uses and defs lists...
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LI = Inst.TheDef->getValueAsListInit("Uses");
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if (!LI->getSize())
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OS << "EmptyImpList, ";
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else
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OS << "ImplicitList" << ListNumbers[LI] << ", ";
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LI = Inst.TheDef->getValueAsListInit("Defs");
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if (!LI->getSize())
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OS << "EmptyImpList, ";
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else
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OS << "ImplicitList" << ListNumbers[LI] << ", ";
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// Emit the operand info.
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std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
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if (OperandInfo.empty())
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OS << "0";
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else
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OS << "OperandInfo" << OpInfo[OperandInfo];
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OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
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}
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void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
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IntInit *ShiftInt, std::ostream &OS) {
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if (Val == 0 || ShiftInt == 0)
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throw std::string("Illegal value or shift amount in TargetInfo*!");
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RecordVal *RV = R->getValue(Val->getValue());
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int Shift = ShiftInt->getValue();
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if (RV == 0 || RV->getValue() == 0)
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throw R->getName() + " doesn't have a field named '" + Val->getValue()+"'!";
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Init *Value = RV->getValue();
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if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
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if (BI->getValue()) OS << "|(1<<" << Shift << ")";
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return;
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} else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
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// Convert the Bits to an integer to print...
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Init *I = BI->convertInitializerTo(new IntRecTy());
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if (I)
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if (IntInit *II = dynamic_cast<IntInit*>(I)) {
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if (II->getValue())
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OS << "|(" << II->getValue() << "<<" << Shift << ")";
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return;
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}
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} else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
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if (II->getValue()) OS << "|(" << II->getValue() << "<<" << Shift << ")";
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return;
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}
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std::cerr << "Unhandled initializer: " << *Val << "\n";
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throw "In record '" + R->getName() + "' for TSFlag emission.";
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}
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