mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-06 09:54:49 +00:00
9de5d0dd42
- Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
9.3 KiB
TableGen
227 lines
9.3 KiB
TableGen
//===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Type profiles and SelectionDAG nodes used by CellSPU
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//
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//===----------------------------------------------------------------------===//
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// Type profile for a call sequence
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def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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// SPU_GenControl: Type profile for generating control words for insertions
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def SPU_GenControl : SDTypeProfile<1, 1, []>;
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def SPUvecinsmask : SDNode<"SPUISD::INSERT_MASK", SPU_GenControl, []>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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// Operand constraints:
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//===----------------------------------------------------------------------===//
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def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// Operand type constraints for vector shuffle/permute operations
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def SDT_SPUshuffle : SDTypeProfile<1, 3, [
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SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
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]>;
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// Unary, binary v16i8 operator type constraints:
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def SPUv16i8_unop: SDTypeProfile<1, 1, [
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SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>]>;
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def SPUv16i8_binop: SDTypeProfile<1, 2, [
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SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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// Binary v8i16 operator type constraints:
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def SPUv8i16_unop: SDTypeProfile<1, 1, [
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SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>]>;
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def SPUv8i16_binop: SDTypeProfile<1, 2, [
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SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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// Binary v4i32 operator type constraints:
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def SPUv4i32_unop: SDTypeProfile<1, 1, [
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SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>]>;
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def SPUv4i32_binop: SDTypeProfile<1, 2, [
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SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
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// FSMBI type constraints: There are several variations for the various
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// vector types (this avoids having to bit_convert all over the place.)
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def SPUfsmbi_type_v16i8: SDTypeProfile<1, 1, [
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SDTCisVT<0, v16i8>, SDTCisVT<1, i32>]>;
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def SPUfsmbi_type_v8i16: SDTypeProfile<1, 1, [
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SDTCisVT<0, v8i16>, SDTCisVT<1, i32>]>;
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def SPUfsmbi_type_v4i32: SDTypeProfile<1, 1, [
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SDTCisVT<0, v4i32>, SDTCisVT<1, i32>]>;
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// SELB type constraints:
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def SPUselb_type_v16i8: SDTypeProfile<1, 3, [
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SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisSameAs<0, 3> ]>;
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def SPUselb_type_v8i16: SDTypeProfile<1, 3, [
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SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisSameAs<0, 3> ]>;
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def SPUselb_type_v4i32: SDTypeProfile<1, 3, [
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SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisSameAs<0, 3> ]>;
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// SPU Vector shift pseudo-instruction type constraints
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def SPUvecshift_type_v16i8: SDTypeProfile<1, 2, [
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SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
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def SPUvecshift_type_v8i16: SDTypeProfile<1, 2, [
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SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
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def SPUvecshift_type_v4i32: SDTypeProfile<1, 2, [
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SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
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//===----------------------------------------------------------------------===//
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// Synthetic/pseudo-instructions
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//===----------------------------------------------------------------------===//
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// SPU CNTB:
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def SPUcntb_v16i8: SDNode<"SPUISD::CNTB", SPUv16i8_unop, []>;
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def SPUcntb_v8i16: SDNode<"SPUISD::CNTB", SPUv8i16_unop, []>;
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def SPUcntb_v4i32: SDNode<"SPUISD::CNTB", SPUv4i32_unop, []>;
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// SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see
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// SPUISelLowering.h):
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def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
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// SPU 16-bit multiply
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def SPUmpy_v16i8: SDNode<"SPUISD::MPY", SPUv16i8_binop, []>;
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def SPUmpy_v8i16: SDNode<"SPUISD::MPY", SPUv8i16_binop, []>;
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def SPUmpy_v4i32: SDNode<"SPUISD::MPY", SPUv4i32_binop, []>;
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// SPU multiply unsigned, used in instruction lowering for v4i32
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// multiplies:
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def SPUmpyu_v4i32: SDNode<"SPUISD::MPYU", SPUv4i32_binop, []>;
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def SPUmpyu_i32: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>;
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// SPU 16-bit multiply high x low, shift result 16-bits
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// Used to compute intermediate products for 32-bit multiplies
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def SPUmpyh_v4i32: SDNode<"SPUISD::MPYH", SPUv4i32_binop, []>;
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def SPUmpyh_i32: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>;
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// SPU 16-bit multiply high x high, 32-bit product
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// Used to compute intermediate products for 16-bit multiplies
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def SPUmpyhh_v8i16: SDNode<"SPUISD::MPYHH", SPUv8i16_binop, []>;
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// Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
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def SPUvec_shl_v8i16: SDNode<"SPUISD::VEC_SHL", SPUvecshift_type_v8i16, []>;
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def SPUvec_srl_v8i16: SDNode<"SPUISD::VEC_SRL", SPUvecshift_type_v8i16, []>;
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def SPUvec_sra_v8i16: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type_v8i16, []>;
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def SPUvec_shl_v4i32: SDNode<"SPUISD::VEC_SHL", SPUvecshift_type_v4i32, []>;
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def SPUvec_srl_v4i32: SDNode<"SPUISD::VEC_SRL", SPUvecshift_type_v4i32, []>;
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def SPUvec_sra_v4i32: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type_v4i32, []>;
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def SPUvec_rotl_v8i16: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type_v8i16, []>;
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def SPUvec_rotl_v4i32: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type_v4i32, []>;
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def SPUvec_rotr_v8i16: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type_v8i16, []>;
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def SPUvec_rotr_v4i32: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type_v4i32, []>;
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def SPUrotbytes_right_zfill: SDNode<"SPUISD::ROTBYTES_RIGHT_Z",
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SPUvecshift_type_v16i8, []>;
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def SPUrotbytes_right_sfill: SDNode<"SPUISD::ROTBYTES_RIGHT_S",
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SPUvecshift_type_v16i8, []>;
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def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
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SPUvecshift_type_v16i8, []>;
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def SPUrotbytes_left_chained : SDNode<"SPUISD::ROTBYTES_LEFT_CHAINED",
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SPUvecshift_type_v16i8, [SDNPHasChain]>;
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// SPU form select mask for bytes, immediate
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def SPUfsmbi_v16i8: SDNode<"SPUISD::FSMBI", SPUfsmbi_type_v16i8, []>;
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def SPUfsmbi_v8i16: SDNode<"SPUISD::FSMBI", SPUfsmbi_type_v8i16, []>;
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def SPUfsmbi_v4i32: SDNode<"SPUISD::FSMBI", SPUfsmbi_type_v4i32, []>;
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// SPU select bits instruction
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def SPUselb_v16i8: SDNode<"SPUISD::SELB", SPUselb_type_v16i8, []>;
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def SPUselb_v8i16: SDNode<"SPUISD::SELB", SPUselb_type_v8i16, []>;
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def SPUselb_v4i32: SDNode<"SPUISD::SELB", SPUselb_type_v4i32, []>;
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// SPU single precision floating point constant load
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def SPUFPconstant: SDNode<"SPUISD::SFPConstant", SDTFPUnaryOp, []>;
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// SPU floating point interpolate
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def SPUinterpolate : SDNode<"SPUISD::FPInterp", SDTFPBinOp, []>;
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// SPU floating point reciprocal estimate (used for fdiv)
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def SPUreciprocalEst: SDNode<"SPUISD::FPRecipEst", SDTFPUnaryOp, []>;
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def SDT_vec_promote : SDTypeProfile<1, 1, []>;
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def SPUpromote_scalar: SDNode<"SPUISD::PROMOTE_SCALAR", SDT_vec_promote, []>;
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def SPU_vec_demote : SDTypeProfile<1, 1, []>;
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def SPUextract_elt0: SDNode<"SPUISD::EXTRACT_ELT0", SPU_vec_demote, []>;
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def SPU_vec_demote_chained : SDTypeProfile<1, 2, []>;
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def SPUextract_elt0_chained: SDNode<"SPUISD::EXTRACT_ELT0_CHAINED",
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SPU_vec_demote_chained, [SDNPHasChain]>;
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def SPUextract_i1_sext: SDNode<"SPUISD::EXTRACT_I1_SEXT", SPU_vec_demote, []>;
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def SPUextract_i1_zext: SDNode<"SPUISD::EXTRACT_I1_ZEXT", SPU_vec_demote, []>;
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def SPUextract_i8_sext: SDNode<"SPUISD::EXTRACT_I8_SEXT", SPU_vec_demote, []>;
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def SPUextract_i8_zext: SDNode<"SPUISD::EXTRACT_I8_ZEXT", SPU_vec_demote, []>;
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// Address high and low components, used for [r+r] type addressing
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def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
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def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
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// PC-relative address
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def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>;
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// A-Form local store addresses
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def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>;
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// D-Form "imm($reg)" addresses
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def SPUdform : SDNode<"SPUISD::DFormAddr", SDTIntBinOp, []>;
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// X-Form "$reg($reg)" addresses
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def SPUxform : SDNode<"SPUISD::XFormAddr", SDTIntBinOp, []>;
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// SPU 32-bit sign-extension to 64-bits
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def SPUsext32_to_64: SDNode<"SPUISD::SEXT32TO64", SDTIntExtendOp, []>;
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// Branches:
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def SPUbrnz : SDNode<"SPUISD::BR_NOTZERO", SDTBrcond, [SDNPHasChain]>;
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def SPUbrz : SDNode<"SPUISD::BR_ZERO", SDTBrcond, [SDNPHasChain]>;
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/* def SPUbinz : SDNode<"SPUISD::BR_NOTZERO", SDTBrind, [SDNPHasChain]>;
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def SPUbiz : SDNode<"SPUISD::BR_ZERO", SPUBrind, [SDNPHasChain]>; */
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//===----------------------------------------------------------------------===//
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// Constraints: (taken from PPCInstrInfo.td)
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//===----------------------------------------------------------------------===//
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class RegConstraint<string C> {
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string Constraints = C;
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}
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class NoEncode<string E> {
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string DisableEncoding = E;
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}
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//===----------------------------------------------------------------------===//
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// Return (flag isn't quite what it means: the operations are flagged so that
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// instruction scheduling doesn't disassociate them.)
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//===----------------------------------------------------------------------===//
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def retflag : SDNode<"SPUISD::RET_FLAG", SDTRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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