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fc989e1ee0
improvements on instruction selection that account for register and frame index bases. Patch contributed by Jeff Cohen. Thanks Jeff! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16110 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
4.2 KiB
C++
113 lines
4.2 KiB
C++
//===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file exposes functions that may be used with BuildMI from the
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// MachineInstrBuilder.h file to handle X86'isms in a clean way.
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//
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// The BuildMem function may be used with the BuildMI function to add entire
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// memory references in a single, typed, function call. X86 memory references
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// can be very complex expressions (described in the README), so wrapping them
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// up behind an easier to use interface makes sense. Descriptions of the
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// functions are included below.
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//
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// For reference, the order of operands for memory references is:
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// (Operand), Base, Scale, Index, Displacement.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRBUILDER_H
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#define X86INSTRBUILDER_H
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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namespace llvm {
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/// X86AddressMode - This struct holds a generalized full x86 address mode.
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/// The base register can be a frame index, which will eventually be replaced
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/// with BP or SP and Disp being offsetted accordingly.
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/// FIXME: add support for globals as a new base type.
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struct X86AddressMode {
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enum {
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UnknownBase,
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RegBase,
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FrameIndexBase
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} BaseType;
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union {
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unsigned Reg;
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int FrameIndex;
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} Base;
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unsigned Scale;
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unsigned IndexReg;
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unsigned Disp;
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X86AddressMode() : BaseType(UnknownBase) {}
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};
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/// addDirectMem - This function is used to add a direct memory reference to the
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/// current instruction -- that is, a dereference of an address in a register,
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/// with no scale, index or displacement. An example is: DWORD PTR [EAX].
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///
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inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
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unsigned Reg) {
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// Because memory references are always represented with four
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// values, this adds: Reg, [1, NoReg, 0] to the instruction.
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return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(0);
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}
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/// addRegOffset - This function is used to add a memory reference of the form
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/// [Reg + Offset], i.e., one with no scale or index, but with a
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/// displacement. An example is: DWORD PTR [EAX + 4].
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///
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inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
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unsigned Reg, int Offset) {
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return MIB.addReg(Reg).addZImm(1).addReg(0).addSImm(Offset);
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}
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inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
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const X86AddressMode &AM) {
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assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
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if (AM.BaseType == X86AddressMode::RegBase)
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MIB.addReg(AM.Base.Reg);
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else if (AM.BaseType == X86AddressMode::FrameIndexBase)
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MIB.addFrameIndex(AM.Base.FrameIndex);
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else
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assert (0);
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return MIB.addZImm(AM.Scale).addReg(AM.IndexReg).addSImm(AM.Disp);
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}
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/// addFrameReference - This function is used to add a reference to the base of
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/// an abstract object on the stack frame of the current function. This
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/// reference has base register as the FrameIndex offset until it is resolved.
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/// This allows a constant offset to be specified as well...
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///
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inline const MachineInstrBuilder &
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addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
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return MIB.addFrameIndex(FI).addZImm(1).addReg(0).addSImm(Offset);
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}
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/// addConstantPoolReference - This function is used to add a reference to the
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/// base of a constant value spilled to the per-function constant pool. The
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/// reference has base register ConstantPoolIndex offset which is retained until
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/// either machine code emission or assembly output. This allows an optional
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/// offset to be added as well.
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///
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inline const MachineInstrBuilder &
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addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
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int Offset = 0) {
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return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset);
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}
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} // End llvm namespace
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#endif
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