Vikram S. Adve 65b2f401af Minor beautification: fold a couple of lines of code. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7054 91177308-0d34-0410-b5e6-96231b3b80d8

2003-07-02 01:24:00 +00:00

..

InstrSched

A def. operand of a machine instruction may be an ordinary Value*,

2003-07-02 01:16:01 +00:00

InstrSelection

Merged in autoconf branch. This provides configuration via the autoconf

2003-06-30 21:59:07 +00:00

Mapping

Moved FInfo.cpp to lib/Target/Sparc as it is Sparc-specific.

2003-06-02 23:27:09 +00:00

ModuloScheduling

add some comments

2003-06-10 20:04:30 +00:00

PostOpts

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PreOpts

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RegAlloc

Minor beautification: fold a couple of lines of code.

2003-07-02 01:24:00 +00:00

LiveVariables.cpp

(1) Added special register class containing (for now) %fsr.

2003-05-27 00:05:23 +00:00

MachineCodeEmitter.cpp

Pass through the emitConstantPool() call to the real emitter.

2003-06-03 20:00:49 +00:00

MachineCodeForInstruction.cpp

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MachineFunction.cpp

Merged in autoconf branch. This provides configuration via the autoconf

2003-06-30 21:59:07 +00:00

MachineInstr.cpp

Allow explicit physical registers for implicit operands.

2003-05-31 07:39:06 +00:00

MachineInstrAnnot.cpp

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Makefile

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PHIElimination.cpp

Fix bug: Jello/2003-06-04-bzip2-bug.ll

2003-06-05 17:15:04 +00:00

PrologEpilogInserter.cpp

(1) Added special register class containing (for now) %fsr.

2003-05-27 00:05:23 +00:00

RegAllocLocal.cpp

(1) Added special register class containing (for now) %fsr.

2003-05-27 00:05:23 +00:00

RegAllocSimple.cpp

(1) Added special register class containing (for now) %fsr.

2003-05-27 00:05:23 +00:00