mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
3.1 KiB
LLVM
98 lines
3.1 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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@b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2
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@float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4
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; FUNC-LABEL: {{^}}float:
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; FIXME: We should be using s_load_dword here.
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; SI: buffer_load_dword
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; EG-DAG: MOV {{\** *}}T2.X
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; EG-DAG: MOV {{\** *}}T3.X
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; EG-DAG: MOV {{\** *}}T4.X
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; EG-DAG: MOV {{\** *}}T5.X
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; EG-DAG: MOV {{\** *}}T6.X
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; EG: MOVA_INT
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define void @float(float addrspace(1)* %out, i32 %index) {
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entry:
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%0 = getelementptr inbounds [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
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%1 = load float addrspace(2)* %0
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store float %1, float addrspace(1)* %out
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ret void
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}
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@i32_gv = internal unnamed_addr addrspace(2) constant [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4], align 4
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; FUNC-LABEL: {{^}}i32:
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; FIXME: We should be using s_load_dword here.
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; SI: buffer_load_dword
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; EG-DAG: MOV {{\** *}}T2.X
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; EG-DAG: MOV {{\** *}}T3.X
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; EG-DAG: MOV {{\** *}}T4.X
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; EG-DAG: MOV {{\** *}}T5.X
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; EG-DAG: MOV {{\** *}}T6.X
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; EG: MOVA_INT
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define void @i32(i32 addrspace(1)* %out, i32 %index) {
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entry:
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%0 = getelementptr inbounds [5 x i32] addrspace(2)* @i32_gv, i32 0, i32 %index
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%1 = load i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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%struct.foo = type { float, [5 x i32] }
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@struct_foo_gv = internal unnamed_addr addrspace(2) constant [1 x %struct.foo] [ %struct.foo { float 16.0, [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4] } ]
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; FUNC-LABEL: {{^}}struct_foo_gv_load:
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; SI: s_load_dword
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define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) {
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%gep = getelementptr inbounds [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index
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%load = load i32 addrspace(2)* %gep, align 4
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store i32 %load, i32 addrspace(1)* %out, align 4
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ret void
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}
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@array_v1_gv = internal addrspace(2) constant [4 x <1 x i32>] [ <1 x i32> <i32 1>,
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<1 x i32> <i32 2>,
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<1 x i32> <i32 3>,
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<1 x i32> <i32 4> ]
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; FUNC-LABEL: {{^}}array_v1_gv_load:
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; FIXME: We should be using s_load_dword here.
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; SI: buffer_load_dword
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define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) {
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%gep = getelementptr inbounds [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index
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%load = load <1 x i32> addrspace(2)* %gep, align 4
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store <1 x i32> %load, <1 x i32> addrspace(1)* %out, align 4
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ret void
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}
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define void @gv_addressing_in_branch(float addrspace(1)* %out, i32 %index, i32 %a) {
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entry:
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%0 = icmp eq i32 0, %a
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br i1 %0, label %if, label %else
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if:
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%1 = getelementptr inbounds [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
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%2 = load float addrspace(2)* %1
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store float %2, float addrspace(1)* %out
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br label %endif
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else:
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store float 1.0, float addrspace(1)* %out
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br label %endif
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endif:
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ret void
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}
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