llvm-6502/test/MC/Mips/mips5
2014-08-15 09:29:30 +00:00
..
invalid-mips32.s [mips] SYNC $stype instruction was added in Mips32 2014-06-18 17:10:30 +00:00
invalid-mips64.s [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier). 2014-06-11 15:05:56 +00:00
invalid-mips64r2-xfail.s [mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2 2014-05-14 15:35:03 +00:00
invalid-mips64r2.s [mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2 2014-05-14 15:35:03 +00:00
valid-xfail.s Current implementation of c.cond.fmt instructions only accept default cc0 register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined. 2014-08-15 09:29:30 +00:00
valid.s Current implementation of c.cond.fmt instructions only accept default cc0 register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined. 2014-08-15 09:29:30 +00:00