mirror of
https://github.com/c64scene-ar/llvm-6502.git
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184f8f7c10
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235616 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
3.9 KiB
LLVM
138 lines
3.9 KiB
LLVM
; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
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; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
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; This is already checked for in Atomics-64.ll
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; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
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; FIXME: we don't currently check for the operations themselves with CHECK-NEXT,
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; because they are implemented in a very messy way with lwarx/stwcx.
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; It should be fixed soon in another patch.
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; We first check loads, for all sizes from i8 to i64.
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; We also vary orderings to check for barriers.
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define i8 @load_i8_unordered(i8* %mem) {
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; CHECK-LABEL: load_i8_unordered
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; CHECK: lbz
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; CHECK-NOT: sync
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%val = load atomic i8, i8* %mem unordered, align 1
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ret i8 %val
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}
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define i16 @load_i16_monotonic(i16* %mem) {
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; CHECK-LABEL: load_i16_monotonic
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; CHECK: lhz
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; CHECK-NOT: sync
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%val = load atomic i16, i16* %mem monotonic, align 2
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ret i16 %val
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}
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define i32 @load_i32_acquire(i32* %mem) {
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; CHECK-LABEL: load_i32_acquire
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; CHECK: lwz
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%val = load atomic i32, i32* %mem acquire, align 4
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; CHECK: lwsync
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ret i32 %val
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}
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define i64 @load_i64_seq_cst(i64* %mem) {
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; CHECK-LABEL: load_i64_seq_cst
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; CHECK: sync 0
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: ld
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%val = load atomic i64, i64* %mem seq_cst, align 8
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; CHECK: lwsync
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ret i64 %val
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}
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; Stores
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define void @store_i8_unordered(i8* %mem) {
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; CHECK-LABEL: store_i8_unordered
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; CHECK-NOT: sync
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; CHECK: stb
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store atomic i8 42, i8* %mem unordered, align 1
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ret void
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}
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define void @store_i16_monotonic(i16* %mem) {
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; CHECK-LABEL: store_i16_monotonic
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; CHECK-NOT: sync
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; CHECK: sth
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store atomic i16 42, i16* %mem monotonic, align 2
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ret void
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}
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define void @store_i32_release(i32* %mem) {
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; CHECK-LABEL: store_i32_release
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; CHECK: lwsync
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; CHECK: stw
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store atomic i32 42, i32* %mem release, align 4
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ret void
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}
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define void @store_i64_seq_cst(i64* %mem) {
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; CHECK-LABEL: store_i64_seq_cst
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; CHECK: sync 0
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; PPC32: __sync_
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; PPC64-NOT: __sync_
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; PPC64: std
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store atomic i64 42, i64* %mem seq_cst, align 8
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ret void
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}
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; Atomic CmpXchg
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define i8 @cas_strong_i8_sc_sc(i8* %mem) {
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; CHECK-LABEL: cas_strong_i8_sc_sc
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; CHECK: sync 0
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%val = cmpxchg i8* %mem, i8 0, i8 1 seq_cst seq_cst
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; CHECK: lwsync
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%loaded = extractvalue { i8, i1} %val, 0
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ret i8 %loaded
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}
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define i16 @cas_weak_i16_acquire_acquire(i16* %mem) {
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; CHECK-LABEL: cas_weak_i16_acquire_acquire
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;CHECK-NOT: sync
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%val = cmpxchg weak i16* %mem, i16 0, i16 1 acquire acquire
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; CHECK: lwsync
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%loaded = extractvalue { i16, i1} %val, 0
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ret i16 %loaded
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}
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define i32 @cas_strong_i32_acqrel_acquire(i32* %mem) {
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; CHECK-LABEL: cas_strong_i32_acqrel_acquire
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; CHECK: lwsync
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%val = cmpxchg i32* %mem, i32 0, i32 1 acq_rel acquire
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; CHECK: lwsync
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%loaded = extractvalue { i32, i1} %val, 0
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ret i32 %loaded
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}
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define i64 @cas_weak_i64_release_monotonic(i64* %mem) {
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; CHECK-LABEL: cas_weak_i64_release_monotonic
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; CHECK: lwsync
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%val = cmpxchg weak i64* %mem, i64 0, i64 1 release monotonic
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; CHECK-NOT: [sync ]
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%loaded = extractvalue { i64, i1} %val, 0
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ret i64 %loaded
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}
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; AtomicRMW
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define i8 @add_i8_monotonic(i8* %mem, i8 %operand) {
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; CHECK-LABEL: add_i8_monotonic
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; CHECK-NOT: sync
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%val = atomicrmw add i8* %mem, i8 %operand monotonic
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ret i8 %val
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}
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define i16 @xor_i16_seq_cst(i16* %mem, i16 %operand) {
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; CHECK-LABEL: xor_i16_seq_cst
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; CHECK: sync 0
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%val = atomicrmw xor i16* %mem, i16 %operand seq_cst
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; CHECK: lwsync
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ret i16 %val
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}
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define i32 @xchg_i32_acq_rel(i32* %mem, i32 %operand) {
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; CHECK-LABEL: xchg_i32_acq_rel
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; CHECK: lwsync
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%val = atomicrmw xchg i32* %mem, i32 %operand acq_rel
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; CHECK: lwsync
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ret i32 %val
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}
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define i64 @and_i64_release(i64* %mem, i64 %operand) {
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; CHECK-LABEL: and_i64_release
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; CHECK: lwsync
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%val = atomicrmw and i64* %mem, i64 %operand release
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; CHECK-NOT: [sync ]
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ret i64 %val
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}
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