mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
7bc4a7ced6
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199391 91177308-0d34-0410-b5e6-96231b3b80d8
246 lines
11 KiB
TableGen
246 lines
11 KiB
TableGen
//===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the Conditional Moves implementation.
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//
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//===----------------------------------------------------------------------===//
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// Conditional moves:
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// These instructions are expanded in
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// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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// conditional move instructions.
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// cond:int, data:int
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class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
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InstrItinClass Itin> :
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InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
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!strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
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let Constraints = "$F = $rd";
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}
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// cond:int, data:float
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class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
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InstrItinClass Itin> :
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InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
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!strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr> {
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let Constraints = "$F = $fd";
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}
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// cond:float, data:int
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class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
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!strconcat(opstr, "\t$rd, $rs, $fcc"),
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[(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
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Itin, FrmFR, opstr> {
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let Constraints = "$F = $rd";
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}
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// cond:float, data:float
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class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
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!strconcat(opstr, "\t$fd, $fs, $fcc"),
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[(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
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Itin, FrmFR, opstr> {
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let Constraints = "$F = $fd";
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}
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// select patterns
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multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction SLTOp,
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Instruction SLTuOp, Instruction SLTiOp,
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Instruction SLTiuOp> {
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def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
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def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
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DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
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def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
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DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
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DRC:$F)>;
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}
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multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction XOROp> {
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def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
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}
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multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction XORiOp> {
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def : MipsPat<
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(select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
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}
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multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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Instruction XOROp> {
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def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
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def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
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def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
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(MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
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}
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// Instantiation of instructions.
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def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
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ADD_FM<0, 0xa>;
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let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
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def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
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ADD_FM<0, 0xa>;
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def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
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ADD_FM<0, 0xa>;
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def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
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ADD_FM<0, 0xa>;
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}
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def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
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ADD_FM<0, 0xb>;
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let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
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def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
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ADD_FM<0, 0xb>;
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def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
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ADD_FM<0, 0xb>;
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def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
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ADD_FM<0, 0xb>;
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}
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def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<18, 16>;
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let isCodeGenOnly = 1 in
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def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>;
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def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<19, 16>;
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let isCodeGenOnly = 1 in
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def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, IIFmove>,
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CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
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IIFmove>, CMov_I_F_FM<18, 17>;
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def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
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IIFmove>, CMov_I_F_FM<19, 17>;
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}
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, IIFmove>,
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CMov_I_F_FM<18, 17>;
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def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, IIFmove>,
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CMov_I_F_FM<19, 17>;
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let isCodeGenOnly = 1 in {
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def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd,
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IIFmove>, CMov_I_F_FM<18, 17>;
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def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd,
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IIFmove>, CMov_I_F_FM<19, 17>;
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}
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}
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def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
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CMov_F_I_FM<1>;
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let isCodeGenOnly = 1 in
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def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
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CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>;
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def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
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CMov_F_I_FM<0>;
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let isCodeGenOnly = 1 in
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def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
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CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>;
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def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<16, 1>;
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def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<16, 0>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, IIFmove,
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MipsCMovFP_T>, CMov_F_F_FM<17, 1>;
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def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove,
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MipsCMovFP_F>, CMov_F_F_FM<17, 0>;
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}
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<17, 0>;
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}
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// Instantiation of conditional move patterns.
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defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>;
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defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>;
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let Predicates = [HasMips64, HasStdEnc] in {
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defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>;
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defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>;
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defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>;
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defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>;
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defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>;
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defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>;
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}
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defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>;
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let Predicates = [HasMips64, HasStdEnc] in {
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defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>;
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defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>;
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defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>;
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}
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defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>;
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defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>;
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let Predicates = [HasMips64, HasStdEnc] in {
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defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>;
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defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>;
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}
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let Predicates = [NotFP64bit, HasStdEnc] in {
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defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>;
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defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>;
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}
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let Predicates = [IsFP64bit, HasStdEnc] in {
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defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>;
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defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>;
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defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>;
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defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>;
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}
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