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https://github.com/c64scene-ar/llvm-6502.git
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4c925c60eb
...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197985 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.2 KiB
TableGen
63 lines
2.2 KiB
TableGen
//===-- SystemZ.td - SystemZ processors and features ---------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Processor and feature definitions.
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//
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//===----------------------------------------------------------------------===//
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class SystemZFeature<string extname, string intname, string desc>
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: Predicate<"Subtarget.has"##intname##"()">,
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AssemblerPredicate<"Feature"##intname, extname>,
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SubtargetFeature<extname, "Has"##intname, "true", desc>;
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class SystemZMissingFeature<string intname>
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: Predicate<"!Subtarget.has"##intname##"()">;
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def FeatureDistinctOps : SystemZFeature<
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"distinct-ops", "DistinctOps",
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"Assume that the distinct-operands facility is installed"
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>;
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def FeatureLoadStoreOnCond : SystemZFeature<
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"load-store-on-cond", "LoadStoreOnCond",
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"Assume that the load/store-on-condition facility is installed"
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>;
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def FeatureHighWord : SystemZFeature<
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"high-word", "HighWord",
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"Assume that the high-word facility is installed"
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>;
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def FeatureFPExtension : SystemZFeature<
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"fp-extension", "FPExtension",
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"Assume that the floating-point extension facility is installed"
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>;
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def FeatureFastSerialization : SystemZFeature<
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"fast-serialization", "FastSerialization",
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"Assume that the fast-serialization facility is installed"
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>;
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def FeatureInterlockedAccess1 : SystemZFeature<
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"interlocked-access1", "InterlockedAccess1",
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"Assume that interlocked-access facility 1 is installed"
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>;
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def FeatureNoInterlockedAccess1 : SystemZMissingFeature<"InterlockedAccess1">;
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def : Processor<"generic", NoItineraries, []>;
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def : Processor<"z10", NoItineraries, []>;
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def : Processor<"z196", NoItineraries,
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[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
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FeatureFPExtension, FeatureFastSerialization,
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FeatureInterlockedAccess1]>;
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def : Processor<"zEC12", NoItineraries,
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[FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
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FeatureFPExtension, FeatureFastSerialization,
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FeatureInterlockedAccess1]>;
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