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3d47855394
So there are a couple of issues with indirect calls on thumbv4t. First, the most 'obvious' instruction, 'blx' isn't available until v5t. And secondly, the next-most-obvious sequence: 'mov lr, pc; bx rN' doesn't DTRT in thumb code because the saved off pc has its thumb bit cleared, so when the callee returns we end up in ARM mode.... yuck. The solution is to 'bl' to a nearby landing pad with a 'bx rN' in it. We could cut down on code size by sharing the landing pads between call sites that are close enough, but for the moment let's do correctness first and look at performance later. Patch by: Iain Sandoe http://reviews.llvm.org/D6519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223380 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.0 KiB
LLVM
41 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=thumbv4t-eabi %s -o - | FileCheck ---check-prefix=CHECK -check-prefix=CHECK-V4T %s
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; RUN: llc -mtriple=thumbv5t-eabi %s -o - | FileCheck ---check-prefix=CHECK -check-prefix=CHECK-V5T %s
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@f = common global void (i32)* null, align 4
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; CHECK-LABEL foo:
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define void @foo(i32 %x) {
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entry:
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%0 = load void (i32)** @f, align 4
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tail call void %0(i32 %x)
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ret void
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; CHECK: ldr [[TMP:r[0-3]]], [[F:\.[A-Z0-9_]+]]
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; CHECK: ldr [[CALLEE:r[0-3]]], {{\[}}[[TMP]]{{\]}}
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; CHECK-V4T-NOT: blx
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; CHECK-V4T: bl [[INDIRECT_PAD:\.Ltmp[0-9]+]]
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; CHECK-V4T: [[F]]:
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; CHECK-V4T: [[INDIRECT_PAD]]:
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; CHECK-V4T-NEXT: bx [[CALLEE]]
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; CHECK-V5T: blx [[CALLEE]]
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}
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; CHECK-LABEL bar:
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define void @bar(void (i32)* nocapture %g, i32 %x, void (i32)* nocapture %h) {
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entry:
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tail call void %g(i32 %x)
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tail call void %h(i32 %x)
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ret void
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; CHECK-V4T: bl [[INDIRECT_PAD1:\.Ltmp[0-9]+]]
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; CHECK-V4T: bl [[INDIRECT_PAD2:\.Ltmp[0-9]+]]
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; CHECK-V4T: [[INDIRECT_PAD1]]:
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; CHECK-V4T-NEXT: bx
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; CHECK-V4T: [[INDIRECT_PAD2]]:
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; CHECK-V4T-NEXT: bx
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; CHECK-V5T: blx
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; CHECK-V5T: blx
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}
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