mirror of
https://github.com/c64scene-ar/llvm-6502.git
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715d98d657
The 'Deprecated' class allows you to specify a SubtargetFeature that the
instruction is deprecated on.
The 'ComplexDeprecationPredicate' class allows you to define a custom
predicate that is called to check for deprecation.
For example:
ComplexDeprecationPredicate<"MCR">
would mean you would have to define the following function:
bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI,
std::string &Info)
Which returns 'false' for not deprecated, and 'true' for deprecated
and store the warning message in 'Info'.
The MCTargetAsmParser constructor was chaned to take an extra argument of
the MCInstrInfo class, so out-of-tree targets will need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
796 lines
27 KiB
C++
796 lines
27 KiB
C++
//===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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// Return true if Expr is in the range [MinValue, MaxValue].
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static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
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int64_t Value = CE->getValue();
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return Value >= MinValue && Value <= MaxValue;
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}
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return false;
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}
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namespace {
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enum RegisterKind {
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GR32Reg,
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GR64Reg,
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GR128Reg,
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ADDR32Reg,
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ADDR64Reg,
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FP32Reg,
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FP64Reg,
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FP128Reg
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};
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enum MemoryKind {
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BDMem,
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BDXMem,
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BDLMem
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};
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class SystemZOperand : public MCParsedAsmOperand {
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public:
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private:
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enum OperandKind {
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KindInvalid,
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KindToken,
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KindReg,
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KindAccessReg,
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KindImm,
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KindMem
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};
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OperandKind Kind;
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SMLoc StartLoc, EndLoc;
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// A string of length Length, starting at Data.
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struct TokenOp {
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const char *Data;
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unsigned Length;
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};
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// LLVM register Num, which has kind Kind. In some ways it might be
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// easier for this class to have a register bank (general, floating-point
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// or access) and a raw register number (0-15). This would postpone the
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// interpretation of the operand to the add*() methods and avoid the need
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// for context-dependent parsing. However, we do things the current way
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// because of the virtual getReg() method, which needs to distinguish
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// between (say) %r0 used as a single register and %r0 used as a pair.
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// Context-dependent parsing can also give us slightly better error
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// messages when invalid pairs like %r1 are used.
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struct RegOp {
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RegisterKind Kind;
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unsigned Num;
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};
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// Base + Disp + Index, where Base and Index are LLVM registers or 0.
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// RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
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// Length is the operand length for D(L,B)-style operands, otherwise
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// it is null.
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struct MemOp {
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unsigned Base : 8;
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unsigned Index : 8;
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unsigned RegKind : 8;
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unsigned Unused : 8;
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const MCExpr *Disp;
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const MCExpr *Length;
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};
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union {
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TokenOp Token;
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RegOp Reg;
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unsigned AccessReg;
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const MCExpr *Imm;
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MemOp Mem;
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};
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SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
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: Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
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{}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible. Null MCExpr = 0.
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if (Expr == 0)
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Inst.addOperand(MCOperand::CreateImm(0));
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else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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public:
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// Create particular kinds of operand.
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static SystemZOperand *createInvalid(SMLoc StartLoc, SMLoc EndLoc) {
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return new SystemZOperand(KindInvalid, StartLoc, EndLoc);
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}
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static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
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SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
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Op->Token.Data = Str.data();
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Op->Token.Length = Str.size();
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return Op;
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}
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static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
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SMLoc StartLoc, SMLoc EndLoc) {
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SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
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Op->Reg.Kind = Kind;
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Op->Reg.Num = Num;
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return Op;
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}
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static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
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SMLoc EndLoc) {
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SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
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Op->AccessReg = Num;
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return Op;
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}
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static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
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SMLoc EndLoc) {
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SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
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Op->Imm = Expr;
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return Op;
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}
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static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
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const MCExpr *Disp, unsigned Index,
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const MCExpr *Length, SMLoc StartLoc,
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SMLoc EndLoc) {
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SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
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Op->Mem.RegKind = RegKind;
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Op->Mem.Base = Base;
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Op->Mem.Index = Index;
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Op->Mem.Disp = Disp;
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Op->Mem.Length = Length;
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return Op;
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}
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// Token operands
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virtual bool isToken() const LLVM_OVERRIDE {
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return Kind == KindToken;
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}
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StringRef getToken() const {
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assert(Kind == KindToken && "Not a token");
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return StringRef(Token.Data, Token.Length);
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}
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// Register operands.
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virtual bool isReg() const LLVM_OVERRIDE {
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return Kind == KindReg;
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}
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bool isReg(RegisterKind RegKind) const {
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return Kind == KindReg && Reg.Kind == RegKind;
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}
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virtual unsigned getReg() const LLVM_OVERRIDE {
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assert(Kind == KindReg && "Not a register");
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return Reg.Num;
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}
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// Access register operands. Access registers aren't exposed to LLVM
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// as registers.
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bool isAccessReg() const {
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return Kind == KindAccessReg;
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}
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// Immediate operands.
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virtual bool isImm() const LLVM_OVERRIDE {
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return Kind == KindImm;
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}
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bool isImm(int64_t MinValue, int64_t MaxValue) const {
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return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
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}
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const MCExpr *getImm() const {
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assert(Kind == KindImm && "Not an immediate");
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return Imm;
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}
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// Memory operands.
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virtual bool isMem() const LLVM_OVERRIDE {
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return Kind == KindMem;
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}
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bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
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return (Kind == KindMem &&
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Mem.RegKind == RegKind &&
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(MemKind == BDXMem || !Mem.Index) &&
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(MemKind == BDLMem) == (Mem.Length != 0));
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}
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bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
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return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
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}
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bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
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return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
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}
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bool isMemDisp12Len8(RegisterKind RegKind) const {
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return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
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}
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// Override MCParsedAsmOperand.
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virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
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virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
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virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
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// Used by the TableGen code to add particular types of operand
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// to an instruction.
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addAccessRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands");
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assert(Kind == KindAccessReg && "Invalid operand type");
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Inst.addOperand(MCOperand::CreateImm(AccessReg));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands");
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addExpr(Inst, getImm());
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}
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void addBDAddrOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands");
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assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
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Inst.addOperand(MCOperand::CreateReg(Mem.Base));
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addExpr(Inst, Mem.Disp);
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}
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void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
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assert(N == 3 && "Invalid number of operands");
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assert(Kind == KindMem && "Invalid operand type");
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Inst.addOperand(MCOperand::CreateReg(Mem.Base));
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addExpr(Inst, Mem.Disp);
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Inst.addOperand(MCOperand::CreateReg(Mem.Index));
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}
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void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
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assert(N == 3 && "Invalid number of operands");
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assert(Kind == KindMem && "Invalid operand type");
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Inst.addOperand(MCOperand::CreateReg(Mem.Base));
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addExpr(Inst, Mem.Disp);
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addExpr(Inst, Mem.Length);
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}
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// Used by the TableGen code to check for particular operand types.
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bool isGR32() const { return isReg(GR32Reg); }
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bool isGR64() const { return isReg(GR64Reg); }
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bool isGR128() const { return isReg(GR128Reg); }
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bool isADDR32() const { return isReg(ADDR32Reg); }
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bool isADDR64() const { return isReg(ADDR64Reg); }
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bool isADDR128() const { return false; }
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bool isFP32() const { return isReg(FP32Reg); }
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bool isFP64() const { return isReg(FP64Reg); }
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bool isFP128() const { return isReg(FP128Reg); }
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bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
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bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
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bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
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bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
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bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
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bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
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bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
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bool isU4Imm() const { return isImm(0, 15); }
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bool isU6Imm() const { return isImm(0, 63); }
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bool isU8Imm() const { return isImm(0, 255); }
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bool isS8Imm() const { return isImm(-128, 127); }
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bool isU16Imm() const { return isImm(0, 65535); }
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bool isS16Imm() const { return isImm(-32768, 32767); }
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bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
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bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
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};
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class SystemZAsmParser : public MCTargetAsmParser {
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#define GET_ASSEMBLER_HEADER
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#include "SystemZGenAsmMatcher.inc"
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private:
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MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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enum RegisterGroup {
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RegGR,
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RegFP,
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RegAccess
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};
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struct Register {
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RegisterGroup Group;
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unsigned Num;
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SMLoc StartLoc, EndLoc;
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};
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bool parseRegister(Register &Reg);
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bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
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bool IsAddress = false);
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OperandMatchResultTy
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parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
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bool parseAddress(unsigned &Base, const MCExpr *&Disp,
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unsigned &Index, const MCExpr *&Length,
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const unsigned *Regs, RegisterKind RegKind);
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OperandMatchResultTy
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parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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const unsigned *Regs, RegisterKind RegKind,
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MemoryKind MemKind);
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bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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StringRef Mnemonic);
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public:
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SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
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const MCInstrInfo &MII)
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: MCTargetAsmParser(), STI(sti), Parser(parser) {
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MCAsmParserExtension::Initialize(Parser);
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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// Override MCTargetAsmParser.
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virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
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virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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SMLoc &EndLoc) LLVM_OVERRIDE;
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virtual bool ParseInstruction(ParseInstructionInfo &Info,
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StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands)
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LLVM_OVERRIDE;
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virtual bool
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MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out, unsigned &ErrorInfo,
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bool MatchingInlineAsm) LLVM_OVERRIDE;
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// Used by the TableGen code to parse particular operand types.
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OperandMatchResultTy
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parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
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}
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OperandMatchResultTy
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parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
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}
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OperandMatchResultTy
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parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
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}
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OperandMatchResultTy
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parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
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}
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OperandMatchResultTy
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parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
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}
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OperandMatchResultTy
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parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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llvm_unreachable("Shouldn't be used as an operand");
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}
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OperandMatchResultTy
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parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
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}
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OperandMatchResultTy
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parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
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}
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OperandMatchResultTy
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parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
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}
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OperandMatchResultTy
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parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
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}
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OperandMatchResultTy
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parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
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}
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OperandMatchResultTy
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parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
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}
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OperandMatchResultTy
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parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
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}
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OperandMatchResultTy
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parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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OperandMatchResultTy
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parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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int64_t MinVal, int64_t MaxVal);
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OperandMatchResultTy
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parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
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}
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OperandMatchResultTy
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parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
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}
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};
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}
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#define GET_REGISTER_MATCHER
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#define GET_SUBTARGET_FEATURE_NAME
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#define GET_MATCHER_IMPLEMENTATION
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#include "SystemZGenAsmMatcher.inc"
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void SystemZOperand::print(raw_ostream &OS) const {
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llvm_unreachable("Not implemented");
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}
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// Parse one register of the form %<prefix><number>.
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bool SystemZAsmParser::parseRegister(Register &Reg) {
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Reg.StartLoc = Parser.getTok().getLoc();
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// Eat the % prefix.
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if (Parser.getTok().isNot(AsmToken::Percent))
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return Error(Parser.getTok().getLoc(), "register expected");
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Parser.Lex();
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// Expect a register name.
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if (Parser.getTok().isNot(AsmToken::Identifier))
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return Error(Reg.StartLoc, "invalid register");
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// Check that there's a prefix.
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StringRef Name = Parser.getTok().getString();
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if (Name.size() < 2)
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return Error(Reg.StartLoc, "invalid register");
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char Prefix = Name[0];
|
|
|
|
// Treat the rest of the register name as a register number.
|
|
if (Name.substr(1).getAsInteger(10, Reg.Num))
|
|
return Error(Reg.StartLoc, "invalid register");
|
|
|
|
// Look for valid combinations of prefix and number.
|
|
if (Prefix == 'r' && Reg.Num < 16)
|
|
Reg.Group = RegGR;
|
|
else if (Prefix == 'f' && Reg.Num < 16)
|
|
Reg.Group = RegFP;
|
|
else if (Prefix == 'a' && Reg.Num < 16)
|
|
Reg.Group = RegAccess;
|
|
else
|
|
return Error(Reg.StartLoc, "invalid register");
|
|
|
|
Reg.EndLoc = Parser.getTok().getLoc();
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
// Parse a register of group Group. If Regs is nonnull, use it to map
|
|
// the raw register number to LLVM numbering, with zero entries indicating
|
|
// an invalid register. IsAddress says whether the register appears in an
|
|
// address context.
|
|
bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
|
|
const unsigned *Regs, bool IsAddress) {
|
|
if (parseRegister(Reg))
|
|
return true;
|
|
if (Reg.Group != Group)
|
|
return Error(Reg.StartLoc, "invalid operand for instruction");
|
|
if (Regs && Regs[Reg.Num] == 0)
|
|
return Error(Reg.StartLoc, "invalid register pair");
|
|
if (Reg.Num == 0 && IsAddress)
|
|
return Error(Reg.StartLoc, "%r0 used in an address");
|
|
if (Regs)
|
|
Reg.Num = Regs[Reg.Num];
|
|
return false;
|
|
}
|
|
|
|
// Parse a register and add it to Operands. The other arguments are as above.
|
|
SystemZAsmParser::OperandMatchResultTy
|
|
SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
RegisterGroup Group, const unsigned *Regs,
|
|
RegisterKind Kind) {
|
|
if (Parser.getTok().isNot(AsmToken::Percent))
|
|
return MatchOperand_NoMatch;
|
|
|
|
Register Reg;
|
|
bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
|
|
if (parseRegister(Reg, Group, Regs, IsAddress))
|
|
return MatchOperand_ParseFail;
|
|
|
|
Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
|
|
Reg.StartLoc, Reg.EndLoc));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
// Parse a memory operand into Base, Disp, Index and Length.
|
|
// Regs maps asm register numbers to LLVM register numbers and RegKind
|
|
// says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
|
|
bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
|
|
unsigned &Index, const MCExpr *&Length,
|
|
const unsigned *Regs,
|
|
RegisterKind RegKind) {
|
|
// Parse the displacement, which must always be present.
|
|
if (getParser().parseExpression(Disp))
|
|
return true;
|
|
|
|
// Parse the optional base and index.
|
|
Index = 0;
|
|
Base = 0;
|
|
Length = 0;
|
|
if (getLexer().is(AsmToken::LParen)) {
|
|
Parser.Lex();
|
|
|
|
if (getLexer().is(AsmToken::Percent)) {
|
|
// Parse the first register and decide whether it's a base or an index.
|
|
Register Reg;
|
|
if (parseRegister(Reg, RegGR, Regs, RegKind))
|
|
return true;
|
|
if (getLexer().is(AsmToken::Comma))
|
|
Index = Reg.Num;
|
|
else
|
|
Base = Reg.Num;
|
|
} else {
|
|
// Parse the length.
|
|
if (getParser().parseExpression(Length))
|
|
return true;
|
|
}
|
|
|
|
// Check whether there's a second register. It's the base if so.
|
|
if (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex();
|
|
Register Reg;
|
|
if (parseRegister(Reg, RegGR, Regs, RegKind))
|
|
return true;
|
|
Base = Reg.Num;
|
|
}
|
|
|
|
// Consume the closing bracket.
|
|
if (getLexer().isNot(AsmToken::RParen))
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in address");
|
|
Parser.Lex();
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// Parse a memory operand and add it to Operands. The other arguments
|
|
// are as above.
|
|
SystemZAsmParser::OperandMatchResultTy
|
|
SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
const unsigned *Regs, RegisterKind RegKind,
|
|
MemoryKind MemKind) {
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
unsigned Base, Index;
|
|
const MCExpr *Disp;
|
|
const MCExpr *Length;
|
|
if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
|
|
return MatchOperand_ParseFail;
|
|
|
|
if (Index && MemKind != BDXMem)
|
|
{
|
|
Error(StartLoc, "invalid use of indexed addressing");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
if (Length && MemKind != BDLMem)
|
|
{
|
|
Error(StartLoc, "invalid use of length addressing");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
if (!Length && MemKind == BDLMem)
|
|
{
|
|
Error(StartLoc, "missing length in address");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
|
|
SMLoc EndLoc =
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
|
|
Length, StartLoc, EndLoc));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
return true;
|
|
}
|
|
|
|
bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
|
|
SMLoc &EndLoc) {
|
|
Register Reg;
|
|
if (parseRegister(Reg))
|
|
return true;
|
|
if (Reg.Group == RegGR)
|
|
RegNo = SystemZMC::GR64Regs[Reg.Num];
|
|
else if (Reg.Group == RegFP)
|
|
RegNo = SystemZMC::FP64Regs[Reg.Num];
|
|
else
|
|
// FIXME: Access registers aren't modelled as LLVM registers yet.
|
|
return Error(Reg.StartLoc, "invalid operand for instruction");
|
|
StartLoc = Reg.StartLoc;
|
|
EndLoc = Reg.EndLoc;
|
|
return false;
|
|
}
|
|
|
|
bool SystemZAsmParser::
|
|
ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
|
|
|
|
// Read the remaining operands.
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
// Read the first operand.
|
|
if (parseOperand(Operands, Name)) {
|
|
Parser.eatToEndOfStatement();
|
|
return true;
|
|
}
|
|
|
|
// Read any subsequent operands.
|
|
while (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex();
|
|
if (parseOperand(Operands, Name)) {
|
|
Parser.eatToEndOfStatement();
|
|
return true;
|
|
}
|
|
}
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
SMLoc Loc = getLexer().getLoc();
|
|
Parser.eatToEndOfStatement();
|
|
return Error(Loc, "unexpected token in argument list");
|
|
}
|
|
}
|
|
|
|
// Consume the EndOfStatement.
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
bool SystemZAsmParser::
|
|
parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
StringRef Mnemonic) {
|
|
// Check if the current operand has a custom associated parser, if so, try to
|
|
// custom parse the operand, or fallback to the general approach.
|
|
OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
|
|
if (ResTy == MatchOperand_Success)
|
|
return false;
|
|
|
|
// If there wasn't a custom match, try the generic matcher below. Otherwise,
|
|
// there was a match, but an error occurred, in which case, just return that
|
|
// the operand parsing failed.
|
|
if (ResTy == MatchOperand_ParseFail)
|
|
return true;
|
|
|
|
// Check for a register. All real register operands should have used
|
|
// a context-dependent parse routine, which gives the required register
|
|
// class. The code is here to mop up other cases, like those where
|
|
// the instruction isn't recognized.
|
|
if (Parser.getTok().is(AsmToken::Percent)) {
|
|
Register Reg;
|
|
if (parseRegister(Reg))
|
|
return true;
|
|
Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
|
|
return false;
|
|
}
|
|
|
|
// The only other type of operand is an immediate or address. As above,
|
|
// real address operands should have used a context-dependent parse routine,
|
|
// so we treat any plain expression as an immediate.
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
unsigned Base, Index;
|
|
const MCExpr *Expr, *Length;
|
|
if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
|
|
return true;
|
|
|
|
SMLoc EndLoc =
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
if (Base || Index || Length)
|
|
Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
|
|
else
|
|
Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
|
|
return false;
|
|
}
|
|
|
|
bool SystemZAsmParser::
|
|
MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
MCStreamer &Out, unsigned &ErrorInfo,
|
|
bool MatchingInlineAsm) {
|
|
MCInst Inst;
|
|
unsigned MatchResult;
|
|
|
|
MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
|
|
MatchingInlineAsm);
|
|
switch (MatchResult) {
|
|
default: break;
|
|
case Match_Success:
|
|
Inst.setLoc(IDLoc);
|
|
Out.EmitInstruction(Inst);
|
|
return false;
|
|
|
|
case Match_MissingFeature: {
|
|
assert(ErrorInfo && "Unknown missing feature!");
|
|
// Special case the error message for the very common case where only
|
|
// a single subtarget feature is missing
|
|
std::string Msg = "instruction requires:";
|
|
unsigned Mask = 1;
|
|
for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
|
|
if (ErrorInfo & Mask) {
|
|
Msg += " ";
|
|
Msg += getSubtargetFeatureName(ErrorInfo & Mask);
|
|
}
|
|
Mask <<= 1;
|
|
}
|
|
return Error(IDLoc, Msg);
|
|
}
|
|
|
|
case Match_InvalidOperand: {
|
|
SMLoc ErrorLoc = IDLoc;
|
|
if (ErrorInfo != ~0U) {
|
|
if (ErrorInfo >= Operands.size())
|
|
return Error(IDLoc, "too few operands for instruction");
|
|
|
|
ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
|
|
if (ErrorLoc == SMLoc())
|
|
ErrorLoc = IDLoc;
|
|
}
|
|
return Error(ErrorLoc, "invalid operand for instruction");
|
|
}
|
|
|
|
case Match_MnemonicFail:
|
|
return Error(IDLoc, "invalid instruction");
|
|
}
|
|
|
|
llvm_unreachable("Unexpected match type");
|
|
}
|
|
|
|
SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
|
|
parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
if (Parser.getTok().isNot(AsmToken::Percent))
|
|
return MatchOperand_NoMatch;
|
|
|
|
Register Reg;
|
|
if (parseRegister(Reg, RegAccess, 0))
|
|
return MatchOperand_ParseFail;
|
|
|
|
Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
|
|
Reg.StartLoc,
|
|
Reg.EndLoc));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
|
|
parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
int64_t MinVal, int64_t MaxVal) {
|
|
MCContext &Ctx = getContext();
|
|
MCStreamer &Out = getStreamer();
|
|
const MCExpr *Expr;
|
|
SMLoc StartLoc = Parser.getTok().getLoc();
|
|
if (getParser().parseExpression(Expr))
|
|
return MatchOperand_NoMatch;
|
|
|
|
// For consistency with the GNU assembler, treat immediates as offsets
|
|
// from ".".
|
|
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
|
|
int64_t Value = CE->getValue();
|
|
if ((Value & 1) || Value < MinVal || Value > MaxVal) {
|
|
Error(StartLoc, "offset out of range");
|
|
return MatchOperand_ParseFail;
|
|
}
|
|
MCSymbol *Sym = Ctx.CreateTempSymbol();
|
|
Out.EmitLabel(Sym);
|
|
const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
|
|
Ctx);
|
|
Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
|
|
}
|
|
|
|
SMLoc EndLoc =
|
|
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeSystemZAsmParser() {
|
|
RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
|
|
}
|