mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
7c7b72a066
This patch adds limited support in ValueTracking for inferring known bits of a value from conditional expressions which must be true to reach the instruction we're trying to optimize. At this time, the feature is off by default. Once landed, I'm hoping for feedback from others on both profitability and compile time impact. Forms of conditional value propagation have been tried in LLVM before and have failed due to compile time problems. In an attempt to side step that, this patch only considers conditions where the edge leaving the branch dominates the context instruction. It does not attempt full dataflow. Even with that restriction, it handles many interesting cases: * Early exits from functions * Early exits from loops (for context instructions in the loop and after the check) * Conditions which control entry into loops, including multi-version loops (such as those produced during vectorization, IRCE, loop unswitch, etc..) Possible applications include optimizing using information provided by constructs such as: preconditions, assumptions, null checks, & range checks. This patch implements two approaches to the problem that need further benchmarking. Approach 1 is to directly walk the dominator tree looking for interesting conditions. Approach 2 is to inspect other uses of the value being queried for interesting comparisons. From initial benchmarking, it appears that Approach 2 is faster than Approach 1, but this needs to be further validated. Differential Revision: http://reviews.llvm.org/D7708 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231879 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
3.2 KiB
LLVM
153 lines
3.2 KiB
LLVM
; RUN: opt -instcombine -value-tracking-dom-conditions=1 -S < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-p1:16:16:16-p2:32:32:32-p3:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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define i1 @test_cmp_ult(i64 %A) {
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; CHECK-LABEL: @test_cmp_ult
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entry:
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%cmp = icmp ult i64 %A, 64
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br i1 %cmp, label %taken, label %untaken
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taken:
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; CHECK-LABEL: taken:
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; CHECK-NEXT: ret i1 false
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%cmp2 = icmp ugt i64 %A, 64
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ret i1 %cmp2
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untaken:
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ret i1 true
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}
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define i1 @test_cmp_ule(i64 %A) {
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; CHECK-LABEL: @test_cmp_ule
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entry:
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%cmp = icmp ule i64 %A, 64
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br i1 %cmp, label %taken, label %untaken
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taken:
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; CHECK-LABEL: taken:
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; CHECK-NEXT: ret i1 false
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%cmp2 = icmp ugt i64 %A, 128
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ret i1 %cmp2
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untaken:
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ret i1 true
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}
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define i1 @test_cmp_sgt(i32 %A) {
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; CHECK-LABEL: @test_cmp_sgt
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entry:
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%cmp = icmp sgt i32 %A, 10
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br i1 %cmp, label %taken, label %untaken
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taken:
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; CHECK-LABEL: taken:
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; CHECK-NEXT: ret i1 true
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%cmp2 = icmp sgt i32 %A, -1
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ret i1 %cmp2
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untaken:
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ret i1 true
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}
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define i64 @test_add_zero_bits(i64 %A) {
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; CHECK-LABEL: @test_add_zero_bits
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entry:
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%cmp = icmp eq i64 %A, 2
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br i1 %cmp, label %taken, label %untaken
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taken:
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; CHECK-LABEL: taken:
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; CHECK-NEXT: ret i64 3
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%add = add i64 %A, 1
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ret i64 %add
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untaken:
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ret i64 %A
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}
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define i64 @test_add_nsw(i64 %A) {
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; CHECK-LABEL: @test_add_nsw
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entry:
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%cmp = icmp ult i64 %A, 20
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br i1 %cmp, label %taken, label %untaken
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taken:
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; CHECK-LABEL: taken:
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; CHECK-NEXT: %add = add nuw nsw i64 %A, 1
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; CHECK-NEXT: ret i64 %add
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%add = add i64 %A, 1
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ret i64 %add
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untaken:
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ret i64 %A
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}
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; After sinking the instructions into the if block, check that we
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; can simplify some of them using dominating conditions.
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define i32 @test_add_zero_bits_sink(i32 %x) nounwind ssp {
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; CHECK-LABEL: @test_add_zero_bits_sink(
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; CHECK-NOT: sdiv i32
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entry:
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%a = add nsw i32 %x, 16
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%b = sdiv i32 %a, %x
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%cmp = icmp ult i32 %x, 7
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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; CHECK-LABEL: bb1:
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; CHECK-NEXT: or i32 %x, 16
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; CHECK-NEXT: udiv i32
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ret i32 %b
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bb2:
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ret i32 %x
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}
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; A condition in the same block gives no information
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define i32 @test_neg1(i32 %x) nounwind ssp {
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; CHECK-LABEL: @test_neg1
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; CHECK: add
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; CHECK: sdiv
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; CHECK: icmp
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; CHECK: select
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entry:
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%a = add nsw i32 %x, 16
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%b = sdiv i32 %a, %x
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%cmp = icmp ult i32 %x, 7
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%ret = select i1 %cmp, i32 %a, i32 %b
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ret i32 %ret
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}
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; A non-dominating edge gives no information
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define i32 @test_neg2(i32 %x) {
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; CHECK-LABEL: @test_neg2
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entry:
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%cmp = icmp ult i32 %x, 7
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br i1 %cmp, label %bb1, label %merge
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bb1:
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br label %merge
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merge:
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; CHECK-LABEL: merge:
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; CHECK: icmp
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; CHECK: select
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%cmp2 = icmp ult i32 %x, 7
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%ret = select i1 %cmp2, i32 %x, i32 0
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ret i32 %ret
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}
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; A unconditional branch expressed as a condition one gives no
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; information (and shouldn't trip any asserts.)
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define i32 @test_neg3(i32 %x) {
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; CHECK-LABEL: @test_neg3
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entry:
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%cmp = icmp ult i32 %x, 7
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br i1 %cmp, label %merge, label %merge
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merge:
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; CHECK-LABEL: merge:
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; CHECK: icmp
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; CHECK: select
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%cmp2 = icmp ult i32 %x, 7
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%ret = select i1 %cmp2, i32 %x, i32 0
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ret i32 %ret
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}
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declare i32 @bar()
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