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This is a follow-on to D8833 (insertps optimization when the zero mask is not used). In this patch, we check for the case where the zmask is used, but both input vectors to the insertps intrinsic are the same operand or the zmask overrides the destination lane. This lets us replace the 2nd shuffle input operand with the zero vector. Differential Revision: http://reviews.llvm.org/D9257 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235810 91177308-0d34-0410-b5e6-96231b3b80d8
151 lines
5.9 KiB
LLVM
151 lines
5.9 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
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; This should never happen, but make sure we don't crash handling a non-constant immediate byte.
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define <4 x float> @insertps_non_const_imm(<4 x float> %v1, <4 x float> %v2, i8 %c) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 %c)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_non_const_imm
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; CHECK-NEXT: call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 %c)
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; CHECK-NEXT: ret <4 x float>
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}
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; If all zero mask bits are set, return a zero regardless of the other control bits.
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define <4 x float> @insertps_0x0f(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 15)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x0f
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; CHECK-NEXT: ret <4 x float> zeroinitializer
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}
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define <4 x float> @insertps_0xff(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 255)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0xff
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; CHECK-NEXT: ret <4 x float> zeroinitializer
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}
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; If some zero mask bits are set that do not override the insertion, we do not change anything.
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define <4 x float> @insertps_0x0c(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 12)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x0c
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; CHECK-NEXT: call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 12)
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; CHECK-NEXT: ret <4 x float>
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}
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; ...unless both input vectors are the same operand.
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define <4 x float> @insertps_0x15_single_input(<4 x float> %v1) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v1, i8 21)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x15_single_input
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> <float 0.000000e+00, float undef, float 0.000000e+00, float undef>, <4 x i32> <i32 4, i32 0, i32 6, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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; The zero mask overrides the insertion lane.
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define <4 x float> @insertps_0x1a_single_input(<4 x float> %v1) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v1, i8 26)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x1a_single_input
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> <float undef, float 0.000000e+00, float undef, float 0.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x float>
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}
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; The zero mask overrides the insertion lane, so the second input vector is not used.
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define <4 x float> @insertps_0xc1(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 193)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0xc1
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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; If no zero mask bits are set, convert to a shuffle.
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define <4 x float> @insertps_0x00(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 0)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x00
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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define <4 x float> @insertps_0x10(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 16)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x10
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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define <4 x float> @insertps_0x20(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 32)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x20
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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define <4 x float> @insertps_0x30(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 48)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0x30
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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; CHECK-NEXT: ret <4 x float>
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}
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define <4 x float> @insertps_0xc0(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 192)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0xc0
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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define <4 x float> @insertps_0xd0(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 208)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0xd0
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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define <4 x float> @insertps_0xe0(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 224)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0xe0
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
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; CHECK-NEXT: ret <4 x float>
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}
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define <4 x float> @insertps_0xf0(<4 x float> %v1, <4 x float> %v2) {
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 240)
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ret <4 x float> %res
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; CHECK-LABEL: @insertps_0xf0
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; CHECK-NEXT: shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x float>
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}
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