Matt Arsenault 2be9044ffc R600/SI: Add additional tests for i1 loads ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222629 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-23 02:57:50 +00:00
..
AArch64	DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same divisor info FMULs by the reciprocal.	2014-11-21 06:39:58 +00:00
ARM	Fix ARM triple parsing	2014-11-17 14:08:57 +00:00
CPP
Generic
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs
Mips	[mips][microMIPS] This patch implements functionality in MIPS delay slot	2014-11-21 22:04:35 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC	[PPC] Use SeparateConstOffsetFromGEP	2014-11-21 04:35:51 +00:00
R600	R600/SI: Add additional tests for i1 loads	2014-11-23 02:57:50 +00:00
SPARC
SystemZ
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2	ARM: allow constpool entry to be moved to the user's block in all cases.	2014-11-13 17:58:53 +00:00
X86	[x86] Add some tests for a common unpack pattern of vector shuffle that	2014-11-22 05:44:43 +00:00
XCore	Fix a bit of confusion about .set and produce more readable assembly.	2014-10-21 01:17:30 +00:00