Elena Demikhovsky ae1ae2c3a1 Masked Vector Load and Store Intrinsics. ... Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-23 08:07:43 +00:00
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Analysis	Revert r222039 because of bot failure.	2014-11-19 00:13:26 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	Masked Vector Load and Store Intrinsics.	2014-11-23 08:07:43 +00:00
DebugInfo	Debug Info: revert r222195, r222210 and r222239.	2014-11-21 19:55:23 +00:00
ExecutionEngine	MCJIT tests passing on ARM after r222414 fixed the relocation	2014-11-20 13:32:16 +00:00
Feature
FileCheck
Instrumentation	[asan] remove old experimental code	2014-11-21 22:34:29 +00:00
Integer
JitListener
Linker	IR: Simplify uniquing for MDNode	2014-11-17 23:28:21 +00:00
LTO
MC	Fix transformation of add with pc argument to adr for non-immediate	2014-11-21 22:39:34 +00:00
Object
Other
SymbolRewriter
TableGen
tools	[ELF] Prevent ARM ELF object writer from generating deprecated relocation code R_ARM_PLT32	2014-11-20 05:58:11 +00:00
Transforms	Masked Vector Load and Store Intrinsics.	2014-11-23 08:07:43 +00:00
Unit
Verifier
YAMLParser
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CMakeLists.txt
lit.cfg
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Makefile.tests
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