Evan Cheng 7189fd03fa Model 128-bit vld lane with REG_SEQUENCE. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103868 91177308-0d34-0410-b5e6-96231b3b80d8

2010-05-15 07:53:37 +00:00

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Analysis

Add support to preserve type info for the variables that are removed by the optimizer.

2010-05-14 21:01:35 +00:00

Archive

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AsmParser

Remove the API compatibility layer which converted add, sub, and mul

2010-05-03 22:44:19 +00:00

Bitcode

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CodeGen

Calculate liveness on the fly for local registers.

2010-05-15 06:09:08 +00:00

CompilerDriver

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ExecutionEngine

Remove the -enable-sjlj-eh option, which doesn't do anything.

2010-05-02 15:36:26 +00:00

Linker

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MC

MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be

2010-05-14 18:53:40 +00:00

Support

Add new configure option, --disable-timestamps, intended to turn off anything which would mess up binary/object comparisons. Currently:

2010-05-10 20:11:56 +00:00

System

Add llvm::sys::RunInterruptHandlers(), which runs the registered SIGINT cleanup

2010-05-08 02:10:34 +00:00

Target

Model 128-bit vld lane with REG_SEQUENCE.

2010-05-15 07:53:37 +00:00

Transforms

Teach the always inliner to release its inline cost estimates, like the basic

2010-05-15 04:26:25 +00:00

VMCore

Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.

2010-05-13 23:55:47 +00:00

Makefile

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