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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
226 lines
8.1 KiB
C++
226 lines
8.1 KiB
C++
//=- llvm/CodeGen/DFAPacketizer.cpp - DFA Packetizer for VLIW -*- C++ -*-=====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
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const unsigned *SET):
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InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
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DFAStateEntryTable(SET) {}
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//
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// ReadTable - Read the DFA transition table and update CachedTable.
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//
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// Format of the transition tables:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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// transitions
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// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable
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// for the ith state
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//
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void DFAPacketizer::ReadTable(unsigned int state) {
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unsigned ThisState = DFAStateEntryTable[state];
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unsigned NextStateInTable = DFAStateEntryTable[state+1];
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// Early exit in case CachedTable has already contains this
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// state's transitions.
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if (CachedTable.count(UnsignPair(state,
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DFAStateInputTable[ThisState][0])))
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return;
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for (unsigned i = ThisState; i < NextStateInTable; i++)
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CachedTable[UnsignPair(state, DFAStateInputTable[i][0])] =
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DFAStateInputTable[i][1];
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state.
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bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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ReadTable(CurrentState);
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return (CachedTable.count(StateTrans) != 0);
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}
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change.
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void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass);
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unsigned FuncUnits = IS->getUnits();
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UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits);
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ReadTable(CurrentState);
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assert(CachedTable.count(StateTrans) != 0);
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CurrentState = CachedTable[StateTrans];
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}
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state.
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bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) {
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const llvm::MCInstrDesc &MID = MI->getDesc();
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return canReserveResources(&MID);
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}
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change.
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void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) {
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const llvm::MCInstrDesc &MID = MI->getDesc();
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reserveResources(&MID);
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}
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namespace llvm {
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// DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
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// Schedule method to build the dependence graph.
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class DefaultVLIWScheduler : public ScheduleDAGInstrs {
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public:
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DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
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MachineDominatorTree &MDT, bool IsPostRA);
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// Schedule - Actual scheduling work.
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void schedule();
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};
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}
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DefaultVLIWScheduler::DefaultVLIWScheduler(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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bool IsPostRA) :
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ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) {
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CanHandleTerminators = true;
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}
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void DefaultVLIWScheduler::schedule() {
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// Build the scheduling graph.
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buildSchedGraph(0);
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}
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// VLIWPacketizerList Ctor
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VLIWPacketizerList::VLIWPacketizerList(
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MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
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bool IsPostRA) : TM(MF.getTarget()), MF(MF) {
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TII = TM.getInstrInfo();
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ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
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VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
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}
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// VLIWPacketizerList Dtor
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VLIWPacketizerList::~VLIWPacketizerList() {
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if (VLIWScheduler)
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delete VLIWScheduler;
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if (ResourceTracker)
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delete ResourceTracker;
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}
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// endPacket - End the current packet, bundle packet instructions and reset
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// DFA state.
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void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
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MachineInstr *MI) {
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if (CurrentPacketMIs.size() > 1) {
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MachineInstr *MIFirst = CurrentPacketMIs.front();
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finalizeBundle(*MBB, MIFirst, MI);
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}
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CurrentPacketMIs.clear();
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ResourceTracker->clearResources();
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}
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// PacketizeMIs - Bundle machine instructions into packets.
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void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator BeginItr,
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MachineBasicBlock::iterator EndItr) {
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assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
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VLIWScheduler->startBlock(MBB);
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VLIWScheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());
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VLIWScheduler->schedule();
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// Generate MI -> SU map.
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MIToSUnit.clear();
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for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
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SUnit *SU = &VLIWScheduler->SUnits[i];
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MIToSUnit[SU->getInstr()] = SU;
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}
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// The main packetizer loop.
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for (; BeginItr != EndItr; ++BeginItr) {
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MachineInstr *MI = BeginItr;
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this->initPacketizerState();
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// End the current packet if needed.
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if (this->isSoloInstruction(MI)) {
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endPacket(MBB, MI);
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continue;
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}
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// Ignore pseudo instructions.
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if (this->ignorePseudoInstruction(MI, MBB))
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continue;
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SUnit *SUI = MIToSUnit[MI];
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assert(SUI && "Missing SUnit Info!");
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// Ask DFA if machine resource is available for MI.
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bool ResourceAvail = ResourceTracker->canReserveResources(MI);
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if (ResourceAvail) {
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// Dependency check for MI with instructions in CurrentPacketMIs.
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for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
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VE = CurrentPacketMIs.end(); VI != VE; ++VI) {
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MachineInstr *MJ = *VI;
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SUnit *SUJ = MIToSUnit[MJ];
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assert(SUJ && "Missing SUnit Info!");
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// Is it legal to packetize SUI and SUJ together.
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if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {
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// Allow packetization if dependency can be pruned.
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if (!this->isLegalToPruneDependencies(SUI, SUJ)) {
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// End the packet if dependency cannot be pruned.
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endPacket(MBB, MI);
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break;
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} // !isLegalToPruneDependencies.
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} // !isLegalToPacketizeTogether.
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} // For all instructions in CurrentPacketMIs.
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} else {
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// End the packet if resource is not available.
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endPacket(MBB, MI);
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}
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// Add MI to the current packet.
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BeginItr = this->addToPacket(MI);
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} // For all instructions in BB.
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// End any packet left behind.
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endPacket(MBB, EndItr);
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VLIWScheduler->exitRegion();
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VLIWScheduler->finishBlock();
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}
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