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We have the same assertion in createVirtualRegister. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176959 91177308-0d34-0410-b5e6-96231b3b80d8
361 lines
12 KiB
C++
361 lines
12 KiB
C++
//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implementation of the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
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: TRI(&TRI), IsSSA(true), TracksLiveness(true) {
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VRegInfo.reserve(256);
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RegAllocHints.reserve(256);
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UsedRegUnits.resize(TRI.getNumRegUnits());
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UsedPhysRegMask.resize(TRI.getNumRegs());
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// Create the physreg use/def lists.
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PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
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memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
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}
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MachineRegisterInfo::~MachineRegisterInfo() {
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delete [] PhysRegUseDefLists;
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}
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/// setRegClass - Set the register class of the specified virtual register.
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///
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void
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MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
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assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
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VRegInfo[Reg].first = RC;
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}
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const TargetRegisterClass *
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MachineRegisterInfo::constrainRegClass(unsigned Reg,
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const TargetRegisterClass *RC,
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unsigned MinNumRegs) {
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const TargetRegisterClass *OldRC = getRegClass(Reg);
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if (OldRC == RC)
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return RC;
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const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
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if (!NewRC || NewRC == OldRC)
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return NewRC;
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if (NewRC->getNumRegs() < MinNumRegs)
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return 0;
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setRegClass(Reg, NewRC);
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return NewRC;
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}
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bool
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MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
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const TargetInstrInfo *TII = TM.getInstrInfo();
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const TargetRegisterClass *OldRC = getRegClass(Reg);
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const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
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// Stop early if there is no room to grow.
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if (NewRC == OldRC)
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return false;
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// Accumulate constraints from all uses.
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for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
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++I) {
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const TargetRegisterClass *OpRC =
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I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
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if (unsigned SubIdx = I.getOperand().getSubReg()) {
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if (OpRC)
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NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
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else
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NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
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} else if (OpRC)
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NewRC = TRI->getCommonSubClass(NewRC, OpRC);
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if (!NewRC || NewRC == OldRC)
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return false;
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}
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setRegClass(Reg, NewRC);
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return true;
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}
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned
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MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
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assert(RegClass && "Cannot create register without RegClass!");
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assert(RegClass->isAllocatable() &&
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"Virtual register RegClass must be allocatable.");
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// New virtual register number.
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unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
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VRegInfo.grow(Reg);
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VRegInfo[Reg].first = RegClass;
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RegAllocHints.grow(Reg);
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return Reg;
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}
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/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
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void MachineRegisterInfo::clearVirtRegs() {
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#ifndef NDEBUG
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for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
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assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
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"Vreg use list non-empty still?");
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#endif
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VRegInfo.clear();
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}
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/// Add MO to the linked list of operands for its register.
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void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
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assert(!MO->isOnRegUseList() && "Already on list");
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MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
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MachineOperand *const Head = HeadRef;
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// Head points to the first list element.
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// Next is NULL on the last list element.
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// Prev pointers are circular, so Head->Prev == Last.
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// Head is NULL for an empty list.
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if (!Head) {
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MO->Contents.Reg.Prev = MO;
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MO->Contents.Reg.Next = 0;
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HeadRef = MO;
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return;
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}
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assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
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// Insert MO between Last and Head in the circular Prev chain.
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MachineOperand *Last = Head->Contents.Reg.Prev;
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assert(Last && "Inconsistent use list");
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assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
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Head->Contents.Reg.Prev = MO;
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MO->Contents.Reg.Prev = Last;
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// Def operands always precede uses. This allows def_iterator to stop early.
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// Insert def operands at the front, and use operands at the back.
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if (MO->isDef()) {
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// Insert def at the front.
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MO->Contents.Reg.Next = Head;
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HeadRef = MO;
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} else {
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// Insert use at the end.
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MO->Contents.Reg.Next = 0;
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Last->Contents.Reg.Next = MO;
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}
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}
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/// Remove MO from its use-def list.
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void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
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assert(MO->isOnRegUseList() && "Operand not on use list");
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MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
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MachineOperand *const Head = HeadRef;
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assert(Head && "List already empty");
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// Unlink this from the doubly linked list of operands.
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MachineOperand *Next = MO->Contents.Reg.Next;
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MachineOperand *Prev = MO->Contents.Reg.Prev;
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// Prev links are circular, next link is NULL instead of looping back to Head.
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if (MO == Head)
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HeadRef = Next;
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else
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Prev->Contents.Reg.Next = Next;
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(Next ? Next : Head)->Contents.Reg.Prev = Prev;
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MO->Contents.Reg.Prev = 0;
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MO->Contents.Reg.Next = 0;
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}
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/// Move NumOps operands from Src to Dst, updating use-def lists as needed.
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///
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/// The Dst range is assumed to be uninitialized memory. (Or it may contain
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/// operands that won't be destroyed, which is OK because the MO destructor is
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/// trivial anyway).
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///
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/// The Src and Dst ranges may overlap.
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void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
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MachineOperand *Src,
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unsigned NumOps) {
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assert(Src != Dst && NumOps && "Noop moveOperands");
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// Copy backwards if Dst is within the Src range.
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int Stride = 1;
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if (Dst >= Src && Dst < Src + NumOps) {
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Stride = -1;
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Dst += NumOps - 1;
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Src += NumOps - 1;
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}
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// Copy one operand at a time.
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do {
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new (Dst) MachineOperand(*Src);
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// Dst takes Src's place in the use-def chain.
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if (Src->isReg()) {
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MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
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MachineOperand *Prev = Src->Contents.Reg.Prev;
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MachineOperand *Next = Src->Contents.Reg.Next;
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assert(Head && "List empty, but operand is chained");
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assert(Prev && "Operand was not on use-def list");
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// Prev links are circular, next link is NULL instead of looping back to
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// Head.
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if (Src == Head)
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Head = Dst;
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else
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Prev->Contents.Reg.Next = Dst;
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// Update Prev pointer. This also works when Src was pointing to itself
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// in a 1-element list. In that case Head == Dst.
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(Next ? Next : Head)->Contents.Reg.Prev = Dst;
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}
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Dst += Stride;
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Src += Stride;
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} while (--NumOps);
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}
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
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assert(FromReg != ToReg && "Cannot replace a reg with itself");
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// TODO: This could be more efficient by bulk changing the operands.
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for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
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MachineOperand &O = I.getOperand();
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++I;
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O.setReg(ToReg);
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}
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}
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/// getVRegDef - Return the machine instr that defines the specified virtual
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/// register or null if none is found. This assumes that the code is in SSA
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/// form, so there should only be one definition.
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MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
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// Since we are in SSA form, we can use the first definition.
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def_iterator I = def_begin(Reg);
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assert((I.atEnd() || llvm::next(I) == def_end()) &&
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"getVRegDef assumes a single definition or no definition");
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return !I.atEnd() ? &*I : 0;
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}
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/// getUniqueVRegDef - Return the unique machine instr that defines the
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/// specified virtual register or null if none is found. If there are
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/// multiple definitions or no definition, return null.
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MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
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if (def_empty(Reg)) return 0;
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def_iterator I = def_begin(Reg);
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if (llvm::next(I) != def_end())
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return 0;
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return &*I;
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}
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bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
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use_nodbg_iterator UI = use_nodbg_begin(RegNo);
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if (UI == use_nodbg_end())
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return false;
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return ++UI == use_nodbg_end();
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}
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/// clearKillFlags - Iterate over all the uses of the given register and
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/// clear the kill flag from the MachineOperand. This function is used by
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/// optimization passes which extend register lifetimes and need only
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/// preserve conservative kill flag information.
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void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
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for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
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UI.getOperand().setIsKill(false);
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}
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bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->first == Reg || I->second == Reg)
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return true;
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return false;
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}
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/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
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/// corresponding live-in physical register.
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unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->second == VReg)
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return I->first;
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return 0;
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}
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/// getLiveInVirtReg - If PReg is a live-in physical register, return the
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/// corresponding live-in physical register.
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unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->first == PReg)
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return I->second;
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return 0;
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}
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/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
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/// into the given entry block.
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void
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MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII) {
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// Emit the copies into the top of the block.
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for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
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if (LiveIns[i].second) {
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if (use_empty(LiveIns[i].second)) {
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// The livein has no uses. Drop it.
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//
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// It would be preferable to have isel avoid creating live-in
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// records for unused arguments in the first place, but it's
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// complicated by the debug info code for arguments.
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LiveIns.erase(LiveIns.begin() + i);
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--i; --e;
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} else {
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// Emit a copy.
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BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
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TII.get(TargetOpcode::COPY), LiveIns[i].second)
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.addReg(LiveIns[i].first);
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// Add the register to the entry block live-in set.
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EntryMBB->addLiveIn(LiveIns[i].first);
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}
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} else {
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// Add the register to the entry block live-in set.
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EntryMBB->addLiveIn(LiveIns[i].first);
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}
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}
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#ifndef NDEBUG
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void MachineRegisterInfo::dumpUses(unsigned Reg) const {
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for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
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I.getOperand().getParent()->dump();
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}
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#endif
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void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
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ReservedRegs = TRI->getReservedRegs(MF);
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assert(ReservedRegs.size() == TRI->getNumRegs() &&
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"Invalid ReservedRegs vector from target");
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}
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bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
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const MachineFunction &MF) const {
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assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
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// Check if any overlapping register is modified, or allocatable so it may be
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// used later.
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for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
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if (!def_empty(*AI) || isAllocatable(*AI))
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return false;
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return true;
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}
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