llvm-6502/test/CodeGen
Jakob Stoklund Olesen f07fc974d3 Reject really weird coalescer case when trying to merge identical subregisters
of different register classes. e.g.

  %reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3

Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.

This should unbreak the dragonegg builder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102672 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29 23:47:46 +00:00
..
Alpha
ARM Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield 2010-04-22 23:24:18 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips
MSP430
PIC16
PowerPC on darwin empty functions need to codegen into something of non-zero length, 2010-04-26 23:37:21 +00:00
SPARC
SystemZ
Thumb
Thumb2 Handle register-to-register copies within the tGPR class. 2010-04-26 23:20:08 +00:00
X86 Reject really weird coalescer case when trying to merge identical subregisters 2010-04-29 23:47:46 +00:00
XCore