llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 04:56:49 +00:00

History

Nate Begeman 2d4c98d79b Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly flag rotate left word immediate then mask insert (rlwimi) as a two-address instruction, and update the ISel usage of the instruction accordingly. This will allow us to properly schedule rlwimi, and use it to efficiently codegen bitfield operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17068 91177308-0d34-0410-b5e6-96231b3b80d8		2004-10-16 20:43:38 +00:00
..
LICENSE.TXT
Makefile	* Make a PPC32-specific code emitter because we have separate classes for 32-	2004-10-14 06:04:56 +00:00
Makefile.am	Update to reflect changes in Makefile rules.	2004-10-13 11:46:52 +00:00
PowerPC.td	PowerPC instruction definitions use LittleEndian-style encoding [0..31]	2004-10-14 05:54:38 +00:00
PowerPCInstrInfo.h
PowerPCRegisterInfo.h
PowerPCTargetMachine.h
PPC32.td	PowerPC instruction definitions use LittleEndian-style encoding [0..31]	2004-10-14 05:54:38 +00:00
PPC32ISelSimple.cpp	Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly	2004-10-16 20:43:38 +00:00
PPC32JITInfo.h
PPC32RegisterInfo.td
PPC64.td	PowerPC instruction definitions use LittleEndian-style encoding [0..31]	2004-10-14 05:54:38 +00:00
PPC64CodeEmitter.cpp
PPC64InstrInfo.cpp
PPC64InstrInfo.h
PPC64ISelSimple.cpp	Several fixes and enhancements to the PPC32 backend.	2004-10-07 22:30:03 +00:00
PPC64JITInfo.h
PPC64RegisterInfo.cpp	Correct some BuildMI arguments for the upcoming simple scheduler	2004-09-27 05:08:17 +00:00
PPC64RegisterInfo.h
PPC64RegisterInfo.td
PPC64TargetMachine.h
PPC.h
PPCAsmPrinter.cpp	add optimized code sequences for setcc x, 0	2004-09-22 04:40:25 +00:00
PPCBranchSelector.cpp	Remove unnecessary header include	2004-10-07 22:24:32 +00:00
PPCCodeEmitter.cpp	* Claim to support machine code emission - return false from	2004-10-14 06:39:56 +00:00
PPCFrameInfo.h
PPCInstrBuilder.h
PPCInstrFormats.td	There is only one field in an instruction, and that is `Inst', the final view of	2004-10-14 05:55:37 +00:00
PPCInstrInfo.cpp	Add ori reg, reg, 0 as a move instruction. This can be generated from	2004-10-07 22:26:12 +00:00
PPCInstrInfo.h
PPCInstrInfo.td	Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly	2004-10-16 20:43:38 +00:00
PPCJITInfo.h
PPCRegisterInfo.cpp	Correct some BuildMI arguments for the upcoming simple scheduler	2004-09-27 05:08:17 +00:00
PPCRegisterInfo.h
PPCRegisterInfo.td	Revamp the Register class, and allow the use of the RegisterGroup class to	2004-09-14 04:17:02 +00:00
PPCTargetMachine.cpp	bling bling!	2004-10-10 16:26:13 +00:00
PPCTargetMachine.h
README.txt

README.txt

TODO:
* implement not-R0 register GPR class
* fix rlwimi generation to be use-and-def
* implement scheduling info
* implement powerpc-64 for darwin
* implement powerpc-64 for aix
* use stfiwx in float->int
* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

Currently failing tests that should pass:
* MultiSource
  |- Applications
  |  `- hbd: miscompilation