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https://github.com/c64scene-ar/llvm-6502.git
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fe532ad6d6
This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183966 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
3.3 KiB
LLVM
138 lines
3.3 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=v7
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=v7
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=v7
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; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
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; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
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; using two shifts.
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; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
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; and therefore must set flags. {{s?}} below denotes this, instead of
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; duplicating tests.
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; zext
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define i8 @zext_1_8(i1 %a) nounwind ssp {
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; v7: zext_1_8:
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; v7: and r0, r0, #1
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; prev6: zext_1_8:
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; prev6: and r0, r0, #1
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%r = zext i1 %a to i8
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ret i8 %r
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}
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define i16 @zext_1_16(i1 %a) nounwind ssp {
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; v7: zext_1_16:
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; v7: and r0, r0, #1
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; prev6: zext_1_16:
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; prev6: and r0, r0, #1
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%r = zext i1 %a to i16
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ret i16 %r
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}
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define i32 @zext_1_32(i1 %a) nounwind ssp {
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; v7: zext_1_32:
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; v7: and r0, r0, #1
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; prev6: zext_1_32:
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; prev6: and r0, r0, #1
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%r = zext i1 %a to i32
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ret i32 %r
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}
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define i16 @zext_8_16(i8 %a) nounwind ssp {
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; v7: zext_8_16:
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; v7: and r0, r0, #255
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; prev6: zext_8_16:
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; prev6: and r0, r0, #255
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%r = zext i8 %a to i16
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ret i16 %r
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}
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define i32 @zext_8_32(i8 %a) nounwind ssp {
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; v7: zext_8_32:
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; v7: and r0, r0, #255
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; prev6: zext_8_32:
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; prev6: and r0, r0, #255
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%r = zext i8 %a to i32
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ret i32 %r
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}
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define i32 @zext_16_32(i16 %a) nounwind ssp {
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; v7: zext_16_32:
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; v7: uxth r0, r0
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; prev6: zext_16_32:
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; prev6: lsl{{s?}} r0, r0, #16
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; prev6: lsr{{s?}} r0, r0, #16
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%r = zext i16 %a to i32
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ret i32 %r
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}
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; sext
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define i8 @sext_1_8(i1 %a) nounwind ssp {
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; v7: sext_1_8:
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; v7: lsl{{s?}} r0, r0, #31
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; v7: asr{{s?}} r0, r0, #31
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; prev6: sext_1_8:
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; prev6: lsl{{s?}} r0, r0, #31
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; prev6: asr{{s?}} r0, r0, #31
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%r = sext i1 %a to i8
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ret i8 %r
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}
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define i16 @sext_1_16(i1 %a) nounwind ssp {
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; v7: sext_1_16:
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; v7: lsl{{s?}} r0, r0, #31
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; v7: asr{{s?}} r0, r0, #31
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; prev6: sext_1_16:
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; prev6: lsl{{s?}} r0, r0, #31
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; prev6: asr{{s?}} r0, r0, #31
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%r = sext i1 %a to i16
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ret i16 %r
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}
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define i32 @sext_1_32(i1 %a) nounwind ssp {
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; v7: sext_1_32:
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; v7: lsl{{s?}} r0, r0, #31
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; v7: asr{{s?}} r0, r0, #31
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; prev6: sext_1_32:
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; prev6: lsl{{s?}} r0, r0, #31
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; prev6: asr{{s?}} r0, r0, #31
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%r = sext i1 %a to i32
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ret i32 %r
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}
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define i16 @sext_8_16(i8 %a) nounwind ssp {
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; v7: sext_8_16:
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; v7: sxtb r0, r0
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; prev6: sext_8_16:
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; prev6: lsl{{s?}} r0, r0, #24
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; prev6: asr{{s?}} r0, r0, #24
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%r = sext i8 %a to i16
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ret i16 %r
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}
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define i32 @sext_8_32(i8 %a) nounwind ssp {
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; v7: sext_8_32:
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; v7: sxtb r0, r0
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; prev6: sext_8_32:
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; prev6: lsl{{s?}} r0, r0, #24
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; prev6: asr{{s?}} r0, r0, #24
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%r = sext i8 %a to i32
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ret i32 %r
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}
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define i32 @sext_16_32(i16 %a) nounwind ssp {
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; v7: sext_16_32:
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; v7: sxth r0, r0
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; prev6: sext_16_32:
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; prev6: lsl{{s?}} r0, r0, #16
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; prev6: asr{{s?}} r0, r0, #16
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%r = sext i16 %a to i32
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ret i32 %r
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}
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