mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
c0021e43ea
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228830 91177308-0d34-0410-b5e6-96231b3b80d8
104 lines
4.6 KiB
LLVM
104 lines
4.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
|
|
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
|
|
|
|
declare float @llvm.fma.f32(float, float, float) #1
|
|
declare float @llvm.fmuladd.f32(float, float, float) #1
|
|
declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) #1
|
|
|
|
|
|
; GCN-LABEL: {{^}}test_sgpr_use_twice_binop:
|
|
; GCN: s_load_dword [[SGPR:s[0-9]+]],
|
|
; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_twice_binop(float addrspace(1)* %out, float %a) #0 {
|
|
%dbl = fadd float %a, %a
|
|
store float %dbl, float addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}test_sgpr_use_three_ternary_op:
|
|
; GCN: s_load_dword [[SGPR:s[0-9]+]],
|
|
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 {
|
|
%fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1
|
|
store float %fma, float addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b:
|
|
; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
|
; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
|
|
; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
|
|
; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
|
|
; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
|
|
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]]
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 {
|
|
%fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1
|
|
store float %fma, float addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a:
|
|
; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
|
; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
|
|
; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
|
|
; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
|
|
; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
|
|
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]]
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 {
|
|
%fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1
|
|
store float %fma, float addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a:
|
|
; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
|
; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
|
|
; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
|
|
; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
|
|
; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]]
|
|
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]]
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 {
|
|
%fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1
|
|
store float %fma, float addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm:
|
|
; GCN: s_load_dword [[SGPR:s[0-9]+]]
|
|
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, float %a) #0 {
|
|
%fma = call float @llvm.fma.f32(float %a, float %a, float 2.0) #1
|
|
store float %fma, float addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a:
|
|
; GCN: s_load_dword [[SGPR:s[0-9]+]]
|
|
; GCN: v_fma_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, float %a) #0 {
|
|
%fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1
|
|
store float %fma, float addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; Don't use fma since fma c, x, y is canonicalized to fma x, c, y
|
|
; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a:
|
|
; GCN: s_load_dword [[SGPR:s[0-9]+]]
|
|
; GCN: v_mad_i32_i24 [[RESULT:v[0-9]+]], 2, [[SGPR]], [[SGPR]]
|
|
; GCN: buffer_store_dword [[RESULT]]
|
|
define void @test_sgpr_use_twice_ternary_op_imm_a_a(i32 addrspace(1)* %out, i32 %a) #0 {
|
|
%fma = call i32 @llvm.AMDGPU.imad24(i32 2, i32 %a, i32 %a) #1
|
|
store i32 %fma, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|