mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
193 lines
4.6 KiB
LLVM
193 lines
4.6 KiB
LLVM
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse42 | FileCheck %s
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; Test based on pr5626 to load/store
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;
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%i32vec3 = type <3 x i32>
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; CHECK: add3i32
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define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
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; CHECK: movdqa
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; CHECK: paddd
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; CHECK: pextrd
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; CHECK: movq
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%a = load %i32vec3* %ap, align 16
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%b = load %i32vec3* %bp, align 16
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%x = add %i32vec3 %a, %b
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store %i32vec3 %x, %i32vec3* %ret, align 16
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ret void
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}
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; CHECK: add3i32_2
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define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) {
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; CHECK: movq
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; CHECK: pinsrd
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; CHECK: movq
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; CHECK: pinsrd
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; CHECK: paddd
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; CHECK: pextrd
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; CHECK: movq
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%a = load %i32vec3* %ap, align 8
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%b = load %i32vec3* %bp, align 8
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%x = add %i32vec3 %a, %b
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store %i32vec3 %x, %i32vec3* %ret, align 8
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ret void
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}
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%i32vec7 = type <7 x i32>
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; CHECK: add7i32
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define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) {
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: paddd
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; CHECK: paddd
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; CHECK: pextrd
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; CHECK: movq
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; CHECK: movdqa
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%a = load %i32vec7* %ap, align 16
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%b = load %i32vec7* %bp, align 16
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%x = add %i32vec7 %a, %b
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store %i32vec7 %x, %i32vec7* %ret, align 16
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ret void
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}
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; CHECK: add12i32
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%i32vec12 = type <12 x i32>
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define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) {
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: paddd
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; CHECK: paddd
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; CHECK: paddd
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: movdqa
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%a = load %i32vec12* %ap, align 16
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%b = load %i32vec12* %bp, align 16
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%x = add %i32vec12 %a, %b
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store %i32vec12 %x, %i32vec12* %ret, align 16
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ret void
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}
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; CHECK: add3i16
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%i16vec3 = type <3 x i16>
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define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
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; CHECK: add3i16
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; CHECK: addl
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; CHECK: addl
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; CHECK: addl
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; CHECK: ret
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%a = load %i16vec3* %ap, align 16
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%b = load %i16vec3* %bp, align 16
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%x = add %i16vec3 %a, %b
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store %i16vec3 %x, %i16vec3* %ret, align 16
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ret void
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}
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; CHECK: add4i16
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%i16vec4 = type <4 x i16>
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define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind {
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; CHECK: add4i16
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; CHECK: paddd
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; CHECK: movq
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%a = load %i16vec4* %ap, align 16
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%b = load %i16vec4* %bp, align 16
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%x = add %i16vec4 %a, %b
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store %i16vec4 %x, %i16vec4* %ret, align 16
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ret void
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}
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; CHECK: add12i16
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%i16vec12 = type <12 x i16>
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define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind {
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: paddw
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; CHECK: paddw
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; CHECK: movq
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; CHECK: movdqa
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%a = load %i16vec12* %ap, align 16
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%b = load %i16vec12* %bp, align 16
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%x = add %i16vec12 %a, %b
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store %i16vec12 %x, %i16vec12* %ret, align 16
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ret void
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}
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; CHECK: add18i16
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%i16vec18 = type <18 x i16>
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define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind {
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: paddw
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; CHECK: paddw
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; CHECK: paddw
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; CHECK: movd
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; CHECK: movdqa
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; CHECK: movdqa
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%a = load %i16vec18* %ap, align 16
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%b = load %i16vec18* %bp, align 16
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%x = add %i16vec18 %a, %b
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store %i16vec18 %x, %i16vec18* %ret, align 16
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ret void
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}
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; CHECK: add3i8
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%i8vec3 = type <3 x i8>
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define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind {
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; CHECK: addb
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; CHECK: addb
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; CHECK: addb
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; CHECK: ret
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%a = load %i8vec3* %ap, align 16
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%b = load %i8vec3* %bp, align 16
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%x = add %i8vec3 %a, %b
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store %i8vec3 %x, %i8vec3* %ret, align 16
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ret void
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}
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; CHECK: add31i8:
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%i8vec31 = type <31 x i8>
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define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
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; CHECK: movdqa
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; CHECK: movdqa
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; CHECK: paddb
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; CHECK: paddb
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; CHECK: movq
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; CHECK: pextrb
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; CHECK: pextrw
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; CHECK: ret
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%a = load %i8vec31* %ap, align 16
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%b = load %i8vec31* %bp, align 16
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%x = add %i8vec31 %a, %b
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store %i8vec31 %x, %i8vec31* %ret, align 16
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ret void
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}
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; CHECK: rot
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%i8vec3pack = type { <3 x i8>, i8 }
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define %i8vec3pack @rot() nounwind {
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; CHECK: movd {{-?[0-9]+}}(%rsp), {{%xmm[0-9]}}
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entry:
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%X = alloca %i8vec3pack, align 4
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%rot = alloca %i8vec3pack, align 4
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%result = alloca %i8vec3pack, align 4
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%storetmp = bitcast %i8vec3pack* %X to <3 x i8>*
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store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp
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%storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>*
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store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1
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%tmp = load %i8vec3pack* %X
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%extractVec = extractvalue %i8vec3pack %tmp, 0
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%tmp2 = load %i8vec3pack* %rot
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%extractVec3 = extractvalue %i8vec3pack %tmp2, 0
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%shr = lshr <3 x i8> %extractVec, %extractVec3
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%storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>*
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store <3 x i8> %shr, <3 x i8>* %storetmp4
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%tmp5 = load %i8vec3pack* %result
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ret %i8vec3pack %tmp5
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}
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