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This is the first incremental patch to implement this feature. It adds no functionality to LLVM but setup up the information needed from targets in order to implement the optimization correctly. Each target needs to specify the maximum number of store operations for conversion of the llvm.memset, llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations. The limit needs to be chosen at the threshold of performance for such an optimization (generally smallish). The target also needs to specify whether the target can support unaligned stores for multi-byte store operations. This helps ensure the optimization doesn't generate code that will trap on an alignment errors. More patches to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22468 91177308-0d34-0410-b5e6-96231b3b80d8
118 lines
4.8 KiB
C++
118 lines
4.8 KiB
C++
//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the TargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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using namespace llvm;
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TargetLowering::TargetLowering(TargetMachine &tm)
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: TM(tm), TD(TM.getTargetData()), ValueTypeActions(0) {
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assert(ISD::BUILTIN_OP_END <= 128 &&
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"Fixed size array in TargetLowering is not large enough!");
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// All operations default to being supported.
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memset(OpActions, 0, sizeof(OpActions));
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IsLittleEndian = TD.isLittleEndian();
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ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
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ShiftAmtHandling = Undefined;
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memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
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maxStoresPerMemSet = maxStoresPerMemCpy = maxStoresPerMemMove = 0;
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allowUnalignedStores = false;
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}
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TargetLowering::~TargetLowering() {}
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/// setValueTypeAction - Set the action for a particular value type. This
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/// assumes an action has not already been set for this value type.
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static void SetValueTypeAction(MVT::ValueType VT,
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TargetLowering::LegalizeAction Action,
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TargetLowering &TLI,
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MVT::ValueType *TransformToType,
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unsigned &ValueTypeActions) {
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ValueTypeActions |= Action << (VT*2);
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if (Action == TargetLowering::Promote) {
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MVT::ValueType PromoteTo;
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if (VT == MVT::f32)
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PromoteTo = MVT::f64;
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else {
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unsigned LargerReg = VT+1;
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while (!TLI.hasNativeSupportFor((MVT::ValueType)LargerReg)) {
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++LargerReg;
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assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
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"Nothing to promote to??");
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}
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PromoteTo = (MVT::ValueType)LargerReg;
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}
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assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
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MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
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"Can only promote from int->int or fp->fp!");
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assert(VT < PromoteTo && "Must promote to a larger type!");
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TransformToType[VT] = PromoteTo;
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} else if (Action == TargetLowering::Expand) {
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assert(MVT::isInteger(VT) && VT > MVT::i8 &&
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"Cannot expand this type: target must support SOME integer reg!");
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// Expand to the next smaller integer type!
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TransformToType[VT] = (MVT::ValueType)(VT-1);
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}
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}
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/// computeRegisterProperties - Once all of the register classes are added,
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/// this allows us to compute derived properties we expose.
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void TargetLowering::computeRegisterProperties() {
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assert(MVT::LAST_VALUETYPE <= 16 &&
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"Too many value types for ValueTypeActions to hold!");
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// Everything defaults to one.
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for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
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NumElementsForVT[i] = 1;
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// Find the largest integer register class.
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unsigned LargestIntReg = MVT::i128;
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for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
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assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
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// Every integer value type larger than this largest register takes twice as
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// many registers to represent as the previous ValueType.
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unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
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for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
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NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
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// Inspect all of the ValueType's possible, deciding how to process them.
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for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
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// If we are expanding this type, expand it!
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if (getNumElements((MVT::ValueType)IntReg) != 1)
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SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
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ValueTypeActions);
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else if (!hasNativeSupportFor((MVT::ValueType)IntReg))
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// Otherwise, if we don't have native support, we must promote to a
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// larger type.
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SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
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TransformToType, ValueTypeActions);
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else
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TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
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// If the target does not have native support for F32, promote it to F64.
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if (!hasNativeSupportFor(MVT::f32))
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SetValueTypeAction(MVT::f32, Promote, *this,
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TransformToType, ValueTypeActions);
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else
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TransformToType[MVT::f32] = MVT::f32;
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assert(hasNativeSupportFor(MVT::f64) && "Target does not support FP?");
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TransformToType[MVT::f64] = MVT::f64;
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}
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