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https://github.com/c64scene-ar/llvm-6502.git
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972f5896e4
- Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
3.0 KiB
C++
81 lines
3.0 KiB
C++
//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MIPS register file
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//===----------------------------------------------------------------------===//
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// We have banks of 32 registers each.
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class MipsReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "Mips";
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}
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// Mips CPU Registers
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class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
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let Num = num;
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}
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// CPU GPR Registers
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def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<0>;
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def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<1>;
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def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<2>;
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def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<3>;
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def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<5>;
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def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<5>;
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def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<6>;
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def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<7>;
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def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<8>;
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def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<9>;
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def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<10>;
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def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<11>;
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def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<12>;
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def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<13>;
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def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<14>;
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def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<15>;
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def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<16>;
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def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<17>;
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def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<18>;
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def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<19>;
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def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<20>;
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def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<21>;
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def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<22>;
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def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<23>;
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def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<24>;
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def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<25>;
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def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<26>;
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def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<27>;
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def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<28>;
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def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<29>;
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def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<30>;
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def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<31>;
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// CPU Registers Class
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def CPURegs : RegisterClass<"Mips", [i32], 32,
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// Return Values and Arguments
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[V0, V1, A0, A1, A2, A3,
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// Not preserved across procedure calls
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T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
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// Callee save
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S0, S1, S2, S3, S4, S5, S6, S7,
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// Reserved
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ZERO, AT, K0, K1, GP, SP, FP, RA]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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CPURegsClass::iterator
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CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
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// The last 8 registers on the list above are reserved
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return end()-8;
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}
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}];
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}
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