mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-29 10:32:47 +00:00
ae16ff1c42
Before this patch, the backend sub-optimally expanded the non-constant shift
count of a v8i16 shift into a sequence of two 'movd' plus 'movzwl'.
With this patch the backend checks if the target features sse4.1. If so, then
it lets the shuffle legalizer deal with the expansion of the shift amount.
Example:
;;
define <8 x i16> @test(<8 x i16> %A, <8 x i16> %B) {
%shamt = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
%shl = shl <8 x i16> %A, %shamt
ret <8 x i16> %shl
}
;;
Before (with -mattr=+avx):
vmovd %xmm1, %eax
movzwl %ax, %eax
vmovd %eax, %xmm1
vpsllw %xmm1, %xmm0, %xmm0
retq
Now:
vpxor %xmm2, %xmm2, %xmm2
vpblendw $1, %xmm1, %xmm2, %xmm1
vpsllw %xmm1, %xmm0, %xmm0
retq
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223660 91177308-0d34-0410-b5e6-96231b3b80d8
150 lines
4.5 KiB
LLVM
150 lines
4.5 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s -check-prefix=SSE2
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s -check-prefix=AVX
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define <8 x i16> @test1(<8 x i16> %A, <8 x i16> %B) {
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; SSE2-LABEL: test1:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %eax
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; SSE2-NEXT: movzwl %ax, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psllw %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test1:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
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; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
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%shl = shl <8 x i16> %A, %vecinit14
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ret <8 x i16> %shl
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}
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define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test2:
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; SSE2: # BB#0
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; SSE2-NEXT: xorps %xmm2, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm2
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; SSE2-NEXT: pslld %xmm2, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test2:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
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; AVX-NEXT: vpslld %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%shl = shl <4 x i32> %A, %vecinit6
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ret <4 x i32> %shl
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}
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define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) {
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; SSE2-LABEL: test3:
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; SSE2: # BB#0
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; SSE2-NEXT: psllq %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test3:
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; AVX: # BB#0
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; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
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%shl = shl <2 x i64> %A, %vecinit2
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ret <2 x i64> %shl
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}
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define <8 x i16> @test4(<8 x i16> %A, <8 x i16> %B) {
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; SSE2-LABEL: test4:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %eax
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; SSE2-NEXT: movzwl %ax, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psrlw %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test4:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
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; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
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%shr = lshr <8 x i16> %A, %vecinit14
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ret <8 x i16> %shr
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}
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define <4 x i32> @test5(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test5:
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; SSE2: # BB#0
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; SSE2-NEXT: xorps %xmm2, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm2
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; SSE2-NEXT: psrld %xmm2, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test5:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
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; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = lshr <4 x i32> %A, %vecinit6
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ret <4 x i32> %shr
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}
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define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) {
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; SSE2-LABEL: test6:
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; SSE2: # BB#0
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; SSE2-NEXT: psrlq %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test6:
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; AVX: # BB#0
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; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit2 = shufflevector <2 x i64> %B, <2 x i64> undef, <2 x i32> zeroinitializer
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%shr = lshr <2 x i64> %A, %vecinit2
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ret <2 x i64> %shr
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}
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define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) {
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; SSE2-LABEL: test7:
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; SSE2: # BB#0
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; SSE2-NEXT: movd %xmm1, %eax
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; SSE2-NEXT: movzwl %ax, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: psraw %xmm1, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test7:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3,4,5,6,7]
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; AVX-NEXT: vpsraw %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit14 = shufflevector <8 x i16> %B, <8 x i16> undef, <8 x i32> zeroinitializer
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%shr = ashr <8 x i16> %A, %vecinit14
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ret <8 x i16> %shr
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}
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define <4 x i32> @test8(<4 x i32> %A, <4 x i32> %B) {
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; SSE2-LABEL: test8:
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; SSE2: # BB#0
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; SSE2-NEXT: xorps %xmm2, %xmm2
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; SSE2-NEXT: movss %xmm1, %xmm2
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; SSE2-NEXT: psrad %xmm2, %xmm0
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; SSE2-NEXT: retq
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; AVX-LABEL: test8:
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; AVX: # BB#0
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; AVX-NEXT: vpxor %xmm2, %xmm2
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
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; AVX-NEXT: vpsrad %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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entry:
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%vecinit6 = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = ashr <4 x i32> %A, %vecinit6
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ret <4 x i32> %shr
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}
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