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https://github.com/c64scene-ar/llvm-6502.git
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3e15bf33e0
Due to darwin gcc bug, one version of darwin linker coalesces static const int, which defauts PassID based pass identification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
825 lines
29 KiB
C++
825 lines
29 KiB
C++
//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the X86 machine instructions into
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// relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86-emitter"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "X86Relocations.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
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const X86InstrInfo *II;
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const TargetData *TD;
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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bool Is64BitMode;
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public:
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static const char ID;
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explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
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: MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
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MCE(mce), Is64BitMode(false) {}
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Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
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const X86InstrInfo &ii, const TargetData &td, bool is64)
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: MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
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MCE(mce), Is64BitMode(is64) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "X86 Machine Code Emitter";
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}
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void emitInstruction(const MachineInstr &MI);
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private:
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void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
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void emitPCRelativeValue(intptr_t Address);
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void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
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void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
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int Disp = 0, unsigned PCAdj = 0);
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
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unsigned PCAdj = 0);
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void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0);
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void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
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unsigned PCAdj = 0);
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void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
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void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
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void emitConstant(uint64_t Val, unsigned Size);
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void emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField,
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unsigned PCAdj = 0);
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unsigned getX86RegNum(unsigned RegNo);
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bool isX86_64ExtendedReg(const MachineOperand &MO);
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unsigned determineREX(const MachineInstr &MI);
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};
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const char Emitter::ID = 0;
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}
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/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
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/// to the specified MCE object.
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FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
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MachineCodeEmitter &MCE) {
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return new Emitter(TM, MCE);
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}
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bool Emitter::runOnMachineFunction(MachineFunction &MF) {
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assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
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MF.getTarget().getRelocationModel() != Reloc::Static) &&
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"JIT relocation model must be set to static or default!");
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II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
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TD = ((X86TargetMachine&)MF.getTarget()).getTargetData();
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Is64BitMode =
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((X86TargetMachine&)MF.getTarget()).getSubtarget<X86Subtarget>().is64Bit();
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do {
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I)
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emitInstruction(*I);
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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/// emitPCRelativeValue - Emit a PC relative address.
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///
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void Emitter::emitPCRelativeValue(intptr_t Address) {
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MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
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}
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/// emitPCRelativeBlockAddress - This method keeps track of the information
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/// necessary to resolve the address of this block later and emits a dummy
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/// value.
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///
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void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
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// Remember where this reference was and where it is to so we can
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// deal with it later.
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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X86::reloc_pcrel_word, MBB));
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MCE.emitWordLE(0);
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}
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/// emitGlobalAddressForCall - Emit the specified address to the code stream
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/// assuming this is part of a function call, which is PC relative.
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///
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void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
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X86::reloc_pcrel_word, GV, 0,
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DoesntNeedStub));
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MCE.emitWordLE(0);
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}
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/// emitGlobalAddress - Emit the specified address to the code stream assuming
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/// this is part of a "take the address of a global" instruction.
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///
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void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
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int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
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GV, PCAdj));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
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}
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/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(0);
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}
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/// emitConstPoolAddress - Arrange for the address of an constant pool
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/// to be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, PCAdj));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
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}
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/// emitJumpTableAddress - Arrange for the address of a jump table to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, JTI, PCAdj));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(0); // The relocated value will be added to the displacement
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}
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/// N86 namespace - Native X86 Register numbers... used by X86 backend.
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///
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namespace N86 {
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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// getX86RegNum - This function maps LLVM register identifiers to their X86
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// specific numbering, which is used in various places encoding instructions.
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//
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unsigned Emitter::getX86RegNum(unsigned RegNo) {
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switch(RegNo) {
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case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
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case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
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case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
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case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
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case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
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return N86::ESP;
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case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
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return N86::EBP;
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case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
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return N86::ESI;
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case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
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return N86::EDI;
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case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
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return N86::EAX;
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case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
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return N86::ECX;
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case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
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return N86::EDX;
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case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
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return N86::EBX;
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case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
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return N86::ESP;
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case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
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return N86::EBP;
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case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
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return N86::ESI;
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case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
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return N86::EDI;
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case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
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case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
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return RegNo-X86::ST0;
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case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
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case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
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return II->getRegisterInfo().getDwarfRegNum(RegNo) -
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II->getRegisterInfo().getDwarfRegNum(X86::XMM0);
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case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
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case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
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return II->getRegisterInfo().getDwarfRegNum(RegNo) -
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II->getRegisterInfo().getDwarfRegNum(X86::XMM8);
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default:
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assert(MRegisterInfo::isVirtualRegister(RegNo) &&
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"Unknown physical register!");
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assert(0 && "Register allocator hasn't allocated reg correctly yet!");
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return 0;
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}
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
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}
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void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
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// SIB byte is in the same format as the ModRMByte...
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MCE.emitByte(ModRMByte(SS, Index, Base));
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}
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void Emitter::emitConstant(uint64_t Val, unsigned Size) {
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// Output the constant in little endian byte order...
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for (unsigned i = 0; i != Size; ++i) {
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MCE.emitByte(Val & 255);
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Val >>= 8;
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}
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}
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/// isDisp8 - Return true if this signed displacement fits in a 8-bit
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/// sign-extended field.
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
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int DispVal, unsigned PCAdj) {
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// If this is a simple integer displacement that doesn't require a relocation,
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// emit it now.
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if (!RelocOp) {
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emitConstant(DispVal, 4);
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return;
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}
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// Otherwise, this is something that requires a relocation. Emit it as such
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// now.
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if (RelocOp->isGlobalAddress()) {
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// In 64-bit static small code model, we could potentially emit absolute.
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// But it's probably not beneficial.
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// 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
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// 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
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unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
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emitGlobalAddressForPtr(RelocOp->getGlobal(), rt,
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RelocOp->getOffset(), PCAdj);
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} else if (RelocOp->isConstantPoolIndex()) {
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// Must be in 64-bit mode.
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emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
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RelocOp->getOffset(), PCAdj);
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} else if (RelocOp->isJumpTableIndex()) {
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// Must be in 64-bit mode.
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emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
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PCAdj);
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} else {
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assert(0 && "Unknown value to relocate!");
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}
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}
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void Emitter::emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField,
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unsigned PCAdj) {
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const MachineOperand &Op3 = MI.getOperand(Op+3);
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int DispVal = 0;
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const MachineOperand *DispForReloc = 0;
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// Figure out what sort of displacement we have to handle here.
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if (Op3.isGlobalAddress()) {
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DispForReloc = &Op3;
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} else if (Op3.isConstantPoolIndex()) {
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if (Is64BitMode) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
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DispVal += Op3.getOffset();
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}
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} else if (Op3.isJumpTableIndex()) {
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if (Is64BitMode) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
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}
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} else {
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DispVal = Op3.getImm();
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}
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const MachineOperand &Base = MI.getOperand(Op);
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const MachineOperand &Scale = MI.getOperand(Op+1);
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const MachineOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = Base.getReg();
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 &&
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(BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
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if (BaseReg == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
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emitDisplacementField(DispForReloc, DispVal, PCAdj);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
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} else if (!DispForReloc && isDisp8(DispVal)) {
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// Emit the disp8 encoding... [REG+disp8]
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MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(DispVal, 1);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
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emitDisplacementField(DispForReloc, DispVal, PCAdj);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP &&
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IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (DispForReloc) {
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// Emit the normal disp32 encoding.
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
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// Emit no displacement ModR/M byte
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding...
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MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding...
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImm()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
|
|
if (ForceDisp8) {
|
|
emitConstant(DispVal, 1);
|
|
} else if (DispVal != 0 || ForceDisp32) {
|
|
emitDisplacementField(DispForReloc, DispVal, PCAdj);
|
|
}
|
|
}
|
|
}
|
|
|
|
static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
|
|
switch (Desc->TSFlags & X86II::ImmMask) {
|
|
case X86II::Imm8: return 1;
|
|
case X86II::Imm16: return 2;
|
|
case X86II::Imm32: return 4;
|
|
case X86II::Imm64: return 8;
|
|
default: assert(0 && "Immediate size not set!");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
|
|
/// e.g. r8, xmm8, etc.
|
|
bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
|
|
if (!MO.isRegister()) return false;
|
|
unsigned RegNo = MO.getReg();
|
|
int DWNum = II->getRegisterInfo().getDwarfRegNum(RegNo);
|
|
if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::R8) &&
|
|
DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::R15))
|
|
return true;
|
|
if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::XMM8) &&
|
|
DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::XMM15))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
inline static bool isX86_64TruncToByte(unsigned oc) {
|
|
return (oc == X86::TRUNC_64to8 || oc == X86::TRUNC_32to8 ||
|
|
oc == X86::TRUNC_16to8);
|
|
}
|
|
|
|
|
|
inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
|
|
return (reg == X86::SPL || reg == X86::BPL ||
|
|
reg == X86::SIL || reg == X86::DIL);
|
|
}
|
|
|
|
/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
|
|
/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
|
|
/// size, and 3) use of X86-64 extended registers.
|
|
unsigned Emitter::determineREX(const MachineInstr &MI) {
|
|
unsigned REX = 0;
|
|
const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
|
|
unsigned Opcode = Desc->Opcode;
|
|
|
|
// Pseudo instructions do not need REX prefix byte.
|
|
if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
|
|
return 0;
|
|
if (Desc->TSFlags & X86II::REX_W)
|
|
REX |= 1 << 3;
|
|
|
|
unsigned NumOps = Desc->numOperands;
|
|
if (NumOps) {
|
|
bool isTwoAddr = NumOps > 1 &&
|
|
Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
|
|
|
|
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
|
|
bool isTrunc8 = isX86_64TruncToByte(Opcode);
|
|
unsigned i = isTwoAddr ? 1 : 0;
|
|
for (unsigned e = NumOps; i != e; ++i) {
|
|
const MachineOperand& MO = MI.getOperand(i);
|
|
if (MO.isRegister()) {
|
|
unsigned Reg = MO.getReg();
|
|
// Trunc to byte are actually movb. The real source operand is the low
|
|
// byte of the register.
|
|
if (isTrunc8 && i == 1)
|
|
Reg = getX86SubSuperRegister(Reg, MVT::i8);
|
|
if (isX86_64NonExtLowByteReg(Reg))
|
|
REX |= 0x40;
|
|
}
|
|
}
|
|
|
|
switch (Desc->TSFlags & X86II::FormMask) {
|
|
case X86II::MRMInitReg:
|
|
if (isX86_64ExtendedReg(MI.getOperand(0)))
|
|
REX |= (1 << 0) | (1 << 2);
|
|
break;
|
|
case X86II::MRMSrcReg: {
|
|
if (isX86_64ExtendedReg(MI.getOperand(0)))
|
|
REX |= 1 << 2;
|
|
i = isTwoAddr ? 2 : 1;
|
|
for (unsigned e = NumOps; i != e; ++i) {
|
|
const MachineOperand& MO = MI.getOperand(i);
|
|
if (isX86_64ExtendedReg(MO))
|
|
REX |= 1 << 0;
|
|
}
|
|
break;
|
|
}
|
|
case X86II::MRMSrcMem: {
|
|
if (isX86_64ExtendedReg(MI.getOperand(0)))
|
|
REX |= 1 << 2;
|
|
unsigned Bit = 0;
|
|
i = isTwoAddr ? 2 : 1;
|
|
for (; i != NumOps; ++i) {
|
|
const MachineOperand& MO = MI.getOperand(i);
|
|
if (MO.isRegister()) {
|
|
if (isX86_64ExtendedReg(MO))
|
|
REX |= 1 << Bit;
|
|
Bit++;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case X86II::MRM0m: case X86II::MRM1m:
|
|
case X86II::MRM2m: case X86II::MRM3m:
|
|
case X86II::MRM4m: case X86II::MRM5m:
|
|
case X86II::MRM6m: case X86II::MRM7m:
|
|
case X86II::MRMDestMem: {
|
|
unsigned e = isTwoAddr ? 5 : 4;
|
|
i = isTwoAddr ? 1 : 0;
|
|
if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
|
|
REX |= 1 << 2;
|
|
unsigned Bit = 0;
|
|
for (; i != e; ++i) {
|
|
const MachineOperand& MO = MI.getOperand(i);
|
|
if (MO.isRegister()) {
|
|
if (isX86_64ExtendedReg(MO))
|
|
REX |= 1 << Bit;
|
|
Bit++;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
default: {
|
|
if (isX86_64ExtendedReg(MI.getOperand(0)))
|
|
REX |= 1 << 0;
|
|
i = isTwoAddr ? 2 : 1;
|
|
for (unsigned e = NumOps; i != e; ++i) {
|
|
const MachineOperand& MO = MI.getOperand(i);
|
|
if (isX86_64ExtendedReg(MO))
|
|
REX |= 1 << 2;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return REX;
|
|
}
|
|
|
|
void Emitter::emitInstruction(const MachineInstr &MI) {
|
|
NumEmitted++; // Keep track of the # of mi's emitted
|
|
|
|
const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
|
|
unsigned Opcode = Desc->Opcode;
|
|
|
|
// Emit the repeat opcode prefix as needed.
|
|
if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
|
|
|
|
// Emit the operand size opcode prefix as needed.
|
|
if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
|
|
|
|
// Emit the address size opcode prefix as needed.
|
|
if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
|
|
|
|
bool Need0FPrefix = false;
|
|
switch (Desc->TSFlags & X86II::Op0Mask) {
|
|
case X86II::TB:
|
|
Need0FPrefix = true; // Two-byte opcode prefix
|
|
break;
|
|
case X86II::T8:
|
|
MCE.emitByte(0x0F);
|
|
MCE.emitByte(0x38);
|
|
break;
|
|
case X86II::TA:
|
|
MCE.emitByte(0x0F);
|
|
MCE.emitByte(0x3A);
|
|
break;
|
|
case X86II::REP: break; // already handled.
|
|
case X86II::XS: // F3 0F
|
|
MCE.emitByte(0xF3);
|
|
Need0FPrefix = true;
|
|
break;
|
|
case X86II::XD: // F2 0F
|
|
MCE.emitByte(0xF2);
|
|
Need0FPrefix = true;
|
|
break;
|
|
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
|
|
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
|
|
MCE.emitByte(0xD8+
|
|
(((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
|
|
>> X86II::Op0Shift));
|
|
break; // Two-byte opcode prefix
|
|
default: assert(0 && "Invalid prefix!");
|
|
case 0: break; // No prefix!
|
|
}
|
|
|
|
if (Is64BitMode) {
|
|
// REX prefix
|
|
unsigned REX = determineREX(MI);
|
|
if (REX)
|
|
MCE.emitByte(0x40 | REX);
|
|
}
|
|
|
|
// 0x0F escape code must be emitted just before the opcode.
|
|
if (Need0FPrefix)
|
|
MCE.emitByte(0x0F);
|
|
|
|
// If this is a two-address instruction, skip one of the register operands.
|
|
unsigned NumOps = Desc->numOperands;
|
|
unsigned CurOp = 0;
|
|
if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
|
|
CurOp++;
|
|
|
|
unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
|
|
switch (Desc->TSFlags & X86II::FormMask) {
|
|
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
|
|
case X86II::Pseudo:
|
|
#ifndef NDEBUG
|
|
switch (Opcode) {
|
|
default:
|
|
assert(0 && "psuedo instructions should be removed before code emission");
|
|
case TargetInstrInfo::INLINEASM:
|
|
assert(0 && "JIT does not support inline asm!\n");
|
|
case TargetInstrInfo::LABEL:
|
|
assert(0 && "JIT does not support meta labels!\n");
|
|
case X86::IMPLICIT_USE:
|
|
case X86::IMPLICIT_DEF:
|
|
case X86::IMPLICIT_DEF_GR8:
|
|
case X86::IMPLICIT_DEF_GR16:
|
|
case X86::IMPLICIT_DEF_GR32:
|
|
case X86::IMPLICIT_DEF_GR64:
|
|
case X86::IMPLICIT_DEF_FR32:
|
|
case X86::IMPLICIT_DEF_FR64:
|
|
case X86::IMPLICIT_DEF_VR64:
|
|
case X86::IMPLICIT_DEF_VR128:
|
|
case X86::FP_REG_KILL:
|
|
break;
|
|
}
|
|
#endif
|
|
CurOp = NumOps;
|
|
break;
|
|
|
|
case X86II::RawFrm:
|
|
MCE.emitByte(BaseOpcode);
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO = MI.getOperand(CurOp++);
|
|
if (MO.isMachineBasicBlock()) {
|
|
emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
|
|
} else if (MO.isGlobalAddress()) {
|
|
bool NeedStub = Is64BitMode ||
|
|
Opcode == X86::TAILJMPd ||
|
|
Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
|
|
emitGlobalAddressForCall(MO.getGlobal(), !NeedStub);
|
|
} else if (MO.isExternalSymbol()) {
|
|
emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
|
|
} else if (MO.isImmediate()) {
|
|
emitConstant(MO.getImm(), sizeOfImm(Desc));
|
|
} else {
|
|
assert(0 && "Unknown RawFrm operand!");
|
|
}
|
|
}
|
|
break;
|
|
|
|
case X86II::AddRegFrm:
|
|
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
|
|
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO1 = MI.getOperand(CurOp++);
|
|
unsigned Size = sizeOfImm(Desc);
|
|
if (MO1.isImmediate())
|
|
emitConstant(MO1.getImm(), Size);
|
|
else {
|
|
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
|
|
if (Opcode == X86::MOV64ri)
|
|
rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
|
|
if (MO1.isGlobalAddress())
|
|
emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
|
|
else if (MO1.isExternalSymbol())
|
|
emitExternalSymbolAddress(MO1.getSymbolName(), rt);
|
|
else if (MO1.isConstantPoolIndex())
|
|
emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
|
|
else if (MO1.isJumpTableIndex())
|
|
emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case X86II::MRMDestReg: {
|
|
MCE.emitByte(BaseOpcode);
|
|
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
|
|
getX86RegNum(MI.getOperand(CurOp+1).getReg()));
|
|
CurOp += 2;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
|
|
break;
|
|
}
|
|
case X86II::MRMDestMem: {
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
|
|
CurOp += 5;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
|
|
break;
|
|
}
|
|
|
|
case X86II::MRMSrcReg:
|
|
MCE.emitByte(BaseOpcode);
|
|
emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
|
|
getX86RegNum(MI.getOperand(CurOp).getReg()));
|
|
CurOp += 2;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
|
|
break;
|
|
|
|
case X86II::MRMSrcMem: {
|
|
unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
|
|
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
|
|
PCAdj);
|
|
CurOp += 5;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
|
|
break;
|
|
}
|
|
|
|
case X86II::MRM0r: case X86II::MRM1r:
|
|
case X86II::MRM2r: case X86II::MRM3r:
|
|
case X86II::MRM4r: case X86II::MRM5r:
|
|
case X86II::MRM6r: case X86II::MRM7r:
|
|
MCE.emitByte(BaseOpcode);
|
|
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
|
|
(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
|
|
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO1 = MI.getOperand(CurOp++);
|
|
unsigned Size = sizeOfImm(Desc);
|
|
if (MO1.isImmediate())
|
|
emitConstant(MO1.getImm(), Size);
|
|
else {
|
|
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
|
|
: X86::reloc_absolute_word;
|
|
if (Opcode == X86::MOV64ri32)
|
|
rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
|
|
if (MO1.isGlobalAddress())
|
|
emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
|
|
else if (MO1.isExternalSymbol())
|
|
emitExternalSymbolAddress(MO1.getSymbolName(), rt);
|
|
else if (MO1.isConstantPoolIndex())
|
|
emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
|
|
else if (MO1.isJumpTableIndex())
|
|
emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case X86II::MRM0m: case X86II::MRM1m:
|
|
case X86II::MRM2m: case X86II::MRM3m:
|
|
case X86II::MRM4m: case X86II::MRM5m:
|
|
case X86II::MRM6m: case X86II::MRM7m: {
|
|
unsigned PCAdj = (CurOp+4 != NumOps) ?
|
|
(MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
|
|
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
|
|
PCAdj);
|
|
CurOp += 4;
|
|
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO = MI.getOperand(CurOp++);
|
|
unsigned Size = sizeOfImm(Desc);
|
|
if (MO.isImmediate())
|
|
emitConstant(MO.getImm(), Size);
|
|
else {
|
|
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
|
|
: X86::reloc_absolute_word;
|
|
if (Opcode == X86::MOV64mi32)
|
|
rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
|
|
if (MO.isGlobalAddress())
|
|
emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset());
|
|
else if (MO.isExternalSymbol())
|
|
emitExternalSymbolAddress(MO.getSymbolName(), rt);
|
|
else if (MO.isConstantPoolIndex())
|
|
emitConstPoolAddress(MO.getConstantPoolIndex(), rt);
|
|
else if (MO.isJumpTableIndex())
|
|
emitJumpTableAddress(MO.getJumpTableIndex(), rt);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case X86II::MRMInitReg:
|
|
MCE.emitByte(BaseOpcode);
|
|
// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
|
|
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
|
|
getX86RegNum(MI.getOperand(CurOp).getReg()));
|
|
++CurOp;
|
|
break;
|
|
}
|
|
|
|
assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
|
|
CurOp == NumOps && "Unknown encoding!");
|
|
}
|