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3f5aa1cd8c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22276 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.6 KiB
TableGen
57 lines
1.6 KiB
TableGen
//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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//Alpha is little endian
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "AlphaRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AlphaInstrInfo.td"
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def AlphaInstrInfo : InstrInfo {
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let PHIInst = PHI;
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// Define how we want to layout our target-specific information field.
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// let TSFlagsFields = [];
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// let TSFlagsShifts = [];
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}
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def Alpha : Target {
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// Pointers on Alpha are 64-bits in size.
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let PointerType = i64;
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let CalleeSavedRegisters =
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//saved regs
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[R9, R10, R11, R12, R13, R14,
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//Frame pointer
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// R15,
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//return address
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// R26,
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//Stack Pointer
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// R30,
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F2, F3, F4, F5, F6, F7, F8, F9];
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// Pull in Instruction Info:
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let InstructionSet = AlphaInstrInfo;
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}
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