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Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
181 lines
7.5 KiB
C++
181 lines
7.5 KiB
C++
//===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// The Hexagon processor has no instructions that load or store predicate
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// registers directly. So, when these registers must be spilled a general
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// purpose register must be found and the value copied to/from it from/to
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// the predicate register. This code currently does not use the register
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// scavenger mechanism available in the allocator. There are two registers
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// reserved to allow spilling/restoring predicate registers. One is used to
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// hold the predicate value. The other is used when stack frame offsets are
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// too large.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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namespace {
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class HexagonExpandPredSpillCode : public MachineFunctionPass {
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HexagonTargetMachine& QTM;
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const HexagonSubtarget &QST;
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public:
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static char ID;
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HexagonExpandPredSpillCode(HexagonTargetMachine& TM) :
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MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
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const char *getPassName() const {
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return "Hexagon Expand Predicate Spill Code";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char HexagonExpandPredSpillCode::ID = 0;
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bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
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const HexagonInstrInfo *TII = QTM.getInstrInfo();
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// Loop over all of the basic blocks.
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for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
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MBBb != MBBe; ++MBBb) {
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MachineBasicBlock* MBB = MBBb;
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// Traverse the basic block.
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for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
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++MII) {
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MachineInstr *MI = MII;
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int Opc = MI->getOpcode();
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if (Opc == Hexagon::STriw_pred) {
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// STriw_pred [R30], ofst, SrcReg;
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unsigned FP = MI->getOperand(0).getReg();
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assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
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"Not a Frame Pointer, Nor a Spill Slot");
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assert(MI->getOperand(1).isImm() && "Not an offset");
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int Offset = MI->getOperand(1).getImm();
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int SrcReg = MI->getOperand(2).getReg();
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assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
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"Not a predicate register");
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if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) {
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if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::CONST32_Int_Real),
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HEXAGON_RESERVED_REG_1).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
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HEXAGON_RESERVED_REG_1)
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.addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
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HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::STriw_indexed))
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0).addReg(HEXAGON_RESERVED_REG_2);
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
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HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
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HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::STriw_indexed))
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0)
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.addReg(HEXAGON_RESERVED_REG_2);
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}
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd),
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HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::STriw_indexed)).
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addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
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}
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MII = MBB->erase(MI);
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--MII;
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} else if (Opc == Hexagon::LDriw_pred) {
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// DstReg = LDriw_pred [R30], ofst.
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int DstReg = MI->getOperand(0).getReg();
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assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
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"Not a predicate register");
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unsigned FP = MI->getOperand(1).getReg();
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assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
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"Not a Frame Pointer, Nor a Spill Slot");
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assert(MI->getOperand(2).isImm() && "Not an offset");
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int Offset = MI->getOperand(2).getImm();
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if (!TII->isValidOffset(Hexagon::LDriw, Offset)) {
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if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {
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BuildMI(*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::CONST32_Int_Real),
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HEXAGON_RESERVED_REG_1).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr),
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HEXAGON_RESERVED_REG_1)
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.addReg(FP)
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.addReg(HEXAGON_RESERVED_REG_1);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
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HEXAGON_RESERVED_REG_2)
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
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DstReg).addReg(HEXAGON_RESERVED_REG_2);
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),
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HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
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HEXAGON_RESERVED_REG_2)
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.addReg(HEXAGON_RESERVED_REG_1)
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.addImm(0);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
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DstReg).addReg(HEXAGON_RESERVED_REG_2);
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}
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} else {
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),
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HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);
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BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs),
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DstReg).addReg(HEXAGON_RESERVED_REG_2);
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}
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MII = MBB->erase(MI);
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--MII;
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}
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}
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}
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return true;
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}
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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FunctionPass *llvm::createHexagonExpandPredSpillCode(HexagonTargetMachine &TM) {
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return new HexagonExpandPredSpillCode(TM);
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}
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