mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
8a712ba229
Before this patch, the backend always emitted a store+load sequence to bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting i64 node was then used to build a v2i32 vector. With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free" bitcast to type MVT::v4i32. The elements of the resulting v4i32 are then extracted to build a v2i32 vector (which is illegal and therefore promoted to MVT::v2i64). This is in general cheaper than emitting a stack store+load sequence to bitconvert the operand from type f64 to type i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208107 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
1.9 KiB
LLVM
81 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 -mattr=+sse2 | FileCheck %s
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define double @test1(double %A) {
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%1 = bitcast double %A to <2 x i32>
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%add = add <2 x i32> %1, <i32 3, i32 5>
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%2 = bitcast <2 x i32> %add to double
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ret double %2
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}
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; FIXME: Ideally we should be able to fold the entire body of @test1 into a
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; single paddd instruction. At the moment we produce the sequence
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; pshufd+paddq+pshufd.
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; CHECK-LABEL: test1
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; CHECK-NOT: movsd
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; CHECK: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define double @test2(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%add = add <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %add to double
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ret double %3
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}
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; FIXME: Ideally we should be able to fold the entire body of @test2 into a
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; single 'paddd %xmm1, %xmm0' instruction. At the moment we produce the
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; sequence pshufd+pshufd+paddq+pshufd.
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; CHECK-LABEL: test2
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; CHECK-NOT: movsd
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; CHECK: pshufd
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define i64 @test3(i64 %A) {
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%1 = bitcast i64 %A to <2 x float>
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%add = fadd <2 x float> %1, <float 3.0, float 5.0>
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%2 = bitcast <2 x float> %add to i64
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ret i64 %2
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: pshufd
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; CHECK: addps
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; CHECK-NOT: pshufd
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; CHECK: ret
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define i64 @test4(i64 %A) {
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%1 = bitcast i64 %A to <2 x i32>
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%add = add <2 x i32> %1, <i32 3, i32 5>
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%2 = bitcast <2 x i32> %add to i64
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ret i64 %2
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}
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; FIXME: At the moment we still produce the sequence pshufd+paddq+pshufd.
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; Ideally, we should fold that sequence into a single paddd.
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; CHECK-LABEL: test4
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; CHECK: pshufd
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; CHECK-NEXT: paddq
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; CHECK-NEXT: pshufd
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; CHECK: ret
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define double @test5(double %A) {
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%1 = bitcast double %A to <2 x float>
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%add = fadd <2 x float> %1, <float 3.0, float 5.0>
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%2 = bitcast <2 x float> %add to double
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ret double %2
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}
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; CHECK-LABEL: test5
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; CHECK: addps
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; CHECK-NEXT: ret
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