mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6ea2b9608a
Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187139 91177308-0d34-0410-b5e6-96231b3b80d8
273 lines
9.7 KiB
LLVM
273 lines
9.7 KiB
LLVM
; These are tests for SSE3 codegen.
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; RUN: llc < %s -march=x86-64 -mcpu=nocona -mtriple=i686-apple-darwin9 -O3 \
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; RUN: | FileCheck %s --check-prefix=X64
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; Test for v8xi16 lowering where we extract the first element of the vector and
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; placed it in the second element of the result.
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define void @t0(<8 x i16>* %dest, <8 x i16>* %old) nounwind {
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entry:
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%tmp3 = load <8 x i16>* %old
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%tmp6 = shufflevector <8 x i16> %tmp3,
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<8 x i16> < i16 0, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef >,
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<8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
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store <8 x i16> %tmp6, <8 x i16>* %dest
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ret void
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; X64-LABEL: t0:
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; X64: movdqa (%rsi), %xmm0
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; X64: pslldq $2, %xmm0
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; X64: movdqa %xmm0, (%rdi)
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; X64: ret
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}
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define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
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ret <8 x i16> %tmp3
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; X64-LABEL: t1:
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; X64: movdqa (%rdi), %xmm0
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; X64: pinsrw $0, (%rsi), %xmm0
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; X64: ret
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}
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define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
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ret <8 x i16> %tmp
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; X64-LABEL: t2:
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; X64: pextrw $1, %xmm1, %eax
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; X64: pinsrw $0, %eax, %xmm0
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; X64: pinsrw $3, %eax, %xmm0
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; X64: ret
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}
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define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
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ret <8 x i16> %tmp
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; X64-LABEL: t3:
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; X64: pextrw $5, %xmm0, %eax
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; X64: pshuflw $44, %xmm0, %xmm0
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; X64: pshufhw $27, %xmm0, %xmm0
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; X64: pinsrw $3, %eax, %xmm0
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; X64: ret
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}
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define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
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ret <8 x i16> %tmp
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; X64-LABEL: t4:
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; X64: pextrw $7, [[XMM0:%xmm[0-9]+]], %eax
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; X64: pshufhw $100, [[XMM0]], [[XMM1:%xmm[0-9]+]]
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; X64: pinsrw $1, %eax, [[XMM1]]
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; X64: pextrw $1, [[XMM0]], %eax
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; X64: pinsrw $4, %eax, %xmm{{[0-9]}}
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; X64: ret
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}
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define <8 x i16> @t5(<8 x i16> %A, <8 x i16> %B) nounwind {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 0, i32 1, i32 10, i32 11, i32 2, i32 3 >
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ret <8 x i16> %tmp
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; X64: t5:
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; X64: movlhps %xmm1, %xmm0
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; X64: pshufd $114, %xmm0, %xmm0
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; X64: ret
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}
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define <8 x i16> @t6(<8 x i16> %A, <8 x i16> %B) nounwind {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
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ret <8 x i16> %tmp
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; X64: t6:
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; X64: movss %xmm1, %xmm0
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; X64: ret
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}
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define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind {
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%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 >
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ret <8 x i16> %tmp
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; X64: t7:
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; X64: pshuflw $-80, %xmm0, %xmm0
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; X64: pshufhw $-56, %xmm0, %xmm0
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; X64: ret
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}
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define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind {
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%tmp = load <2 x i64>* %A
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%tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16>
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%tmp0 = extractelement <8 x i16> %tmp.upgrd.1, i32 0
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%tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1
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%tmp2 = extractelement <8 x i16> %tmp.upgrd.1, i32 2
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%tmp3 = extractelement <8 x i16> %tmp.upgrd.1, i32 3
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%tmp4 = extractelement <8 x i16> %tmp.upgrd.1, i32 4
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%tmp5 = extractelement <8 x i16> %tmp.upgrd.1, i32 5
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%tmp6 = extractelement <8 x i16> %tmp.upgrd.1, i32 6
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%tmp7 = extractelement <8 x i16> %tmp.upgrd.1, i32 7
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%tmp8 = insertelement <8 x i16> undef, i16 %tmp2, i32 0
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%tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 1
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%tmp10 = insertelement <8 x i16> %tmp9, i16 %tmp0, i32 2
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%tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 3
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%tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp6, i32 4
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%tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 5
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%tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp4, i32 6
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%tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 7
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%tmp15.upgrd.2 = bitcast <8 x i16> %tmp15 to <2 x i64>
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store <2 x i64> %tmp15.upgrd.2, <2 x i64>* %res
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ret void
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; X64: t8:
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; X64: pshuflw $-58, (%rsi), %xmm0
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; X64: pshufhw $-58, %xmm0, %xmm0
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; X64: movdqa %xmm0, (%rdi)
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; X64: ret
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}
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define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
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%tmp = load <4 x float>* %r
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%tmp.upgrd.3 = bitcast <2 x i32>* %A to double*
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%tmp.upgrd.4 = load double* %tmp.upgrd.3
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%tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0
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%tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1
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%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>
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%tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0
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%tmp7 = extractelement <4 x float> %tmp, i32 1
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%tmp8 = extractelement <4 x float> %tmp6, i32 0
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%tmp9 = extractelement <4 x float> %tmp6, i32 1
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%tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0
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%tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1
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%tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2
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%tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3
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store <4 x float> %tmp13, <4 x float>* %r
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ret void
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; X64: t9:
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; X64: movaps (%rdi), %xmm0
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; X64: movhps (%rsi), %xmm0
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; X64: movaps %xmm0, (%rdi)
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; X64: ret
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}
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; FIXME: This testcase produces icky code. It can be made much better!
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; PR2585
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@g1 = external constant <4 x i32>
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@g2 = external constant <4 x i16>
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define internal void @t10() nounwind {
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load <4 x i32>* @g1, align 16
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bitcast <4 x i32> %1 to <8 x i16>
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shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef >
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bitcast <8 x i16> %3 to <2 x i64>
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extractelement <2 x i64> %4, i32 0
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bitcast i64 %5 to <4 x i16>
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store <4 x i16> %6, <4 x i16>* @g2, align 8
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ret void
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; X64: t10:
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; X64: pextrw $4, [[X0:%xmm[0-9]+]], %e{{..}}
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; X64: pextrw $6, [[X0]], %e{{..}}
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; X64: movlhps [[X0]], [[X0]]
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; X64: pshuflw $8, [[X0]], [[X0]]
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; X64: pinsrw $2, %e{{..}}, [[X0]]
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; X64: pinsrw $3, %e{{..}}, [[X0]]
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}
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; Pack various elements via shuffles.
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define <8 x i16> @t11(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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entry:
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%tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
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ret <8 x i16> %tmp7
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; X64-LABEL: t11:
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; X64: movd %xmm1, %eax
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; X64: movlhps %xmm0, %xmm0
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; X64: pshuflw $1, %xmm0, %xmm0
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; X64: pinsrw $1, %eax, %xmm0
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; X64: ret
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}
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define <8 x i16> @t12(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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entry:
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%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef >
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ret <8 x i16> %tmp9
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; X64-LABEL: t12:
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; X64: pextrw $3, %xmm1, %eax
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; X64: movlhps %xmm0, %xmm0
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; X64: pshufhw $3, %xmm0, %xmm0
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; X64: pinsrw $5, %eax, %xmm0
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; X64: ret
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}
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define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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entry:
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%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef >
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ret <8 x i16> %tmp9
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; X64-LABEL: t13:
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; X64: punpcklqdq %xmm0, %xmm1
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; X64: pextrw $3, %xmm1, %eax
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; X64: pshufd $52, %xmm1, %xmm0
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; X64: pinsrw $4, %eax, %xmm0
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; X64: ret
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}
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define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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entry:
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%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef >
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ret <8 x i16> %tmp9
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; X64-LABEL: t14:
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; X64: punpcklqdq %xmm0, %xmm1
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; X64: pshufhw $8, %xmm1, %xmm0
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; X64: ret
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}
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; FIXME: t15 is worse off from disabling of scheduler 2-address hack.
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define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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entry:
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%tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
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ret <8 x i16> %tmp8
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; X64: t15:
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; X64: pextrw $7, %xmm0, %eax
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; X64: punpcklqdq %xmm1, %xmm0
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; X64: pshuflw $-128, %xmm0, %xmm0
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; X64: pinsrw $2, %eax, %xmm0
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; X64: ret
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}
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; Test yonah where we convert a shuffle to pextrw and pinrsw
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define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone {
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entry:
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%tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
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%tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
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ret <16 x i8> %tmp9
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; X64: t16:
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; X64: pextrw $8, %xmm0, %eax
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; X64: pslldq $2, %xmm0
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; X64: pextrw $1, %xmm0, %ecx
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; X64: movzbl %cl, %ecx
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; X64: orl %eax, %ecx
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; X64: pinsrw $1, %ecx, %xmm0
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; X64: ret
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}
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; rdar://8520311
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define <4 x i32> @t17() nounwind {
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entry:
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; X64-LABEL: t17:
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; X64: movddup (%rax), %xmm0
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%tmp1 = load <4 x float>* undef, align 16
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
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%tmp3 = load <4 x float>* undef, align 16
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%tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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%tmp5 = bitcast <4 x float> %tmp3 to <4 x i32>
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%tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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%tmp7 = and <4 x i32> %tmp6, <i32 undef, i32 undef, i32 -1, i32 0>
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ret <4 x i32> %tmp7
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}
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