David Blaikie 6d9dbd5526 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions ... Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184066 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-16 20:34:15 +00:00
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AArch64	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
ARM	Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions	2013-06-16 20:34:15 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
MBlaze	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
Mips	[mips] Add an IR transformation pass that optimizes calls to sqrt.	2013-06-11 22:21:44 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Remove old CONST_NOT_GEN address space that is not being used anymore and causes constants to be emitted in the global address space	2013-06-10 13:29:47 +00:00
PowerPC	[PowerPC] Disable fast-isel for existing -O0 tests for PowerPC.	2013-06-13 20:23:34 +00:00
R600	R600: Add SI load support for v[24]i32 and store for v2i32	2013-06-15 00:09:31 +00:00
SI
SPARC	[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.	2013-06-08 15:32:59 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	DebugInfo: follow up to 184045 to constrain the tests further to ensure they don't contain +0 offsets	2013-06-15 16:02:44 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00