David Woodhouse 7360e8caa3 [x86] Fix 16-bit handling of OpSize bit ... When disassembling in 16-bit mode the meaning of the OpSize bit is inverted. Instructions found in the IC_OPSIZE context will actually *not* have the 0x66 prefix, and instructions in the IC context will have the 0x66 prefix. Make use of the existing special-case handling for the 0x66 prefix being in the wrong place, to cope with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199650 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-20 12:02:35 +00:00
..
AArch64	[AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point zero in asm parser.	2014-01-20 02:14:05 +00:00
ARM	ARM: add tlsldo relocation	2014-01-20 11:00:40 +00:00
AsmParser	Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.	2014-01-05 01:35:51 +00:00
COFF	WinCOFF: Transform IR expressions featuring __ImageBase into image relative relocations	2014-01-15 09:16:42 +00:00
Disassembler	[x86] Fix 16-bit handling of OpSize bit	2014-01-20 12:02:35 +00:00
ELF	Force emit a relocation for @gnu_indirect_function symbols so that the indirect	2014-01-08 18:50:32 +00:00
MachO
Markup
Mips	Added support for LWU microMIPS instruction.	2014-01-15 13:01:18 +00:00
PowerPC
Sparc	[Sparc] Add support for parsing floating point instructions.	2014-01-12 04:48:54 +00:00
SystemZ	[SystemZ] Add MC support for interlocked-access 1 instructions	2013-12-24 15:14:05 +00:00
X86	[x86] Support i386-*-*-code16 triple for emitting 16-bit code	2014-01-20 12:02:25 +00:00