Toma Tabacu 739ca842aa [mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol. ... Summary: Even though there is no 2nd register operand in the "lw/sw $8, symbol" case, we still try to find one, and we end up with $0, which makes us generate an unnecessary "addu $8, $8, $0" (a.k.a. "move $8, $8"). We can avoid this by checking if the 2nd register operand is different from $0, before generating the addu. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8055 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234406 91177308-0d34-0410-b5e6-96231b3b80d8		2015-04-08 13:52:41 +00:00
..
AArch64	AArch64: disallow "fmov sD, #-0.0" during assembly.	2015-04-07 22:49:47 +00:00
ARM	Write the section header in the end.	2015-04-08 11:41:24 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Disassembler	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
ELF	Write the section header in the end.	2015-04-08 11:41:24 +00:00
Hexagon	Expand MUX instructions early on Hexagon	2015-03-31 13:35:12 +00:00
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-04-03 01:46:11 +00:00
Markup
Mips	[mips] [IAS] Do not generate redundant move when expanding lw/sw with symbol.	2015-04-08 13:52:41 +00:00
PowerPC	[PowerPC] Add asm parser support for bitmask forms of rotate-and-mask instructions	2015-03-28 19:42:41 +00:00
R600	R600/SI: Initial support for assembler and inline assembly	2015-04-08 01:09:26 +00:00
Sparc
SystemZ	[SystemZ] Support transactional execution on zEC12	2015-04-01 12:51:43 +00:00
X86	Fix the operand encoding in the test instruction.	2015-03-31 12:31:55 +00:00