mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c0021e43ea
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228830 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
2.1 KiB
LLVM
62 lines
2.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}fneg_f64:
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; GCN: v_xor_b32
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define void @fneg_f64(double addrspace(1)* %out, double %in) {
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%fneg = fsub double -0.000000e+00, %in
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store double %fneg, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_v2f64:
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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define void @fneg_v2f64(<2 x double> addrspace(1)* nocapture %out, <2 x double> %in) {
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%fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
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store <2 x double> %fneg, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_v4f64:
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; R600: -PV
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; R600: -T
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; R600: -PV
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; R600: -PV
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double> %in) {
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%fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %in
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store <4 x double> %fneg, <4 x double> addrspace(1)* %out
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ret void
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}
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; DAGCombiner will transform:
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; (fneg (f64 bitcast (i64 a))) => (f64 bitcast (xor (i64 a), 0x80000000))
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; unless the target returns true for isNegFree()
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; FUNC-LABEL: {{^}}fneg_free_f64:
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; FIXME: Unnecessary copy to VGPRs
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; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]$}}
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define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fsub = fsub double 0.0, %bc
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fold_f64:
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; SI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; VI: s_load_dwordx2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN-NOT: xor
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; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], [[NEG_VALUE]]
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define void @fneg_fold_f64(double addrspace(1)* %out, double %in) {
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%fsub = fsub double -0.0, %in
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%fmul = fmul double %fsub, %in
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store double %fmul, double addrspace(1)* %out
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ret void
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}
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