mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 05:32:25 +00:00
c0021e43ea
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228830 91177308-0d34-0410-b5e6-96231b3b80d8
88 lines
3.0 KiB
LLVM
88 lines
3.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s
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; When a frame index offset is more than 12-bits, make sure we don't store
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; it in mubuf's offset field.
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; Also, make sure we use the same register for storing the scratch buffer addresss
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; for both stores. This register is allocated by the register scavenger, so we
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; should be able to reuse the same regiser for each scratch buffer access.
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; CHECK-LABEL: {{^}}legal_offset_fi:
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; CHECK: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0{{$}}
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; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen
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; CHECK: v_mov_b32_e32 [[OFFSET]], 0x8000
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; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}}
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define void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) {
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entry:
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%scratch0 = alloca [8192 x i32]
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%scratch1 = alloca [8192 x i32]
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%scratchptr0 = getelementptr [8192 x i32]* %scratch0, i32 0, i32 0
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store i32 1, i32* %scratchptr0
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%scratchptr1 = getelementptr [8192 x i32]* %scratch1, i32 0, i32 0
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store i32 2, i32* %scratchptr1
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else
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if:
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%if_ptr = getelementptr [8192 x i32]* %scratch0, i32 0, i32 %if_offset
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%if_value = load i32* %if_ptr
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br label %done
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else:
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%else_ptr = getelementptr [8192 x i32]* %scratch1, i32 0, i32 %else_offset
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%else_value = load i32* %else_ptr
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br label %done
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done:
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%value = phi i32 [%if_value, %if], [%else_value, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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ret void
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}
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; CHECK-LABEL: {{^}}legal_offset_fi_offset
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; CHECK: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen
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; CHECK: v_add_i32_e32 [[OFFSET:v[0-9]+]], 0x8000
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; CHECK: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}}
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define void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) {
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entry:
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%scratch0 = alloca [8192 x i32]
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%scratch1 = alloca [8192 x i32]
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%offset0 = load i32 addrspace(1)* %offsets
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%scratchptr0 = getelementptr [8192 x i32]* %scratch0, i32 0, i32 %offset0
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store i32 %offset0, i32* %scratchptr0
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%offsetptr1 = getelementptr i32 addrspace(1)* %offsets, i32 1
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%offset1 = load i32 addrspace(1)* %offsetptr1
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%scratchptr1 = getelementptr [8192 x i32]* %scratch1, i32 0, i32 %offset1
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store i32 %offset1, i32* %scratchptr1
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else
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if:
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%if_ptr = getelementptr [8192 x i32]* %scratch0, i32 0, i32 %if_offset
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%if_value = load i32* %if_ptr
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br label %done
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else:
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%else_ptr = getelementptr [8192 x i32]* %scratch1, i32 0, i32 %else_offset
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%else_value = load i32* %else_ptr
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br label %done
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done:
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%value = phi i32 [%if_value, %if], [%else_value, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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