mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-29 11:29:39 +00:00
73c2f7f5ed
This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
116 lines
2.3 KiB
LLVM
116 lines
2.3 KiB
LLVM
; RUN: llc < %s -march=x86 -mcpu=pentiumpro | FileCheck %s
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define i32 @f(i32 %X) {
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entry:
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; CHECK: f:
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; CHECK: jns
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%tmp1 = add i32 %X, 1 ; <i32> [#uses=1]
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%tmp = icmp slt i32 %tmp1, 0 ; <i1> [#uses=1]
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br i1 %tmp, label %cond_true, label %cond_next
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cond_true: ; preds = %entry
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%tmp2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0]
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br label %cond_next
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cond_next: ; preds = %cond_true, %entry
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%tmp3 = tail call i32 (...)* @baz( ) ; <i32> [#uses=0]
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ret i32 undef
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}
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declare i32 @bar(...)
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declare i32 @baz(...)
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; rdar://10633221
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; rdar://11355268
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define i32 @g(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: g:
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; CHECK-NOT: test
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; CHECK: cmovs
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%sub = sub nsw i32 %a, %b
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%cmp = icmp sgt i32 %sub, 0
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; rdar://10734411
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define i32 @h(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: h:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @i(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: i:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @j(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: j:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp ugt i32 %a, %b
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @k(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: k:
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; CHECK-NOT: cmp
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; CHECK: cmov
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; CHECK-NOT: movl
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; CHECK: ret
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%cmp = icmp ult i32 %b, %a
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; redundant cmp instruction
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define i32 @l(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: l:
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; CHECK-NOT: cmp
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 %a
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ret i32 %cond
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}
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define i32 @m(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: m:
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; CHECK-NOT: cmp
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %b, i32 %sub
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ret i32 %cond
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}
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; rdar://11540023
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define i64 @n(i64 %x, i64 %y) nounwind {
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entry:
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; CHECK: n:
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; CHECK-NOT: sub
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; CHECK: cmp
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%sub = sub nsw i64 %x, %y
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%cmp = icmp slt i64 %sub, 0
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%y.x = select i1 %cmp, i64 %y, i64 %x
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ret i64 %y.x
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}
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