Jakob Stoklund Olesen 73e7dced38 Add an isSSA() flag to MachineRegisterInfo. ... This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136532 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-29 22:51:22 +00:00
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Analysis
Archive
AsmParser
Bitcode
CodeGen	Add an isSSA() flag to MachineRegisterInfo.	2011-07-29 22:51:22 +00:00
CompilerDriver
ExecutionEngine
Linker
MC	On mac, it seems the MC disassembler is actually using the targetinfo	2011-07-29 20:23:34 +00:00
Object
Support
Target	Add support for the 'Q' constraint.	2011-07-29 21:18:58 +00:00
Transforms
VMCore	have the verifier catch gep's into opaque struct types. PR10473	2011-07-29 20:32:28 +00:00
CMakeLists.txt
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