mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7a9ef44b3b
Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
2.9 KiB
LLVM
87 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
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; rdar://7353541
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; rdar://7354376
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; The generated code is no where near ideal. It's not recognizing the two
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; constantpool entries being loaded can be merged into one.
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@GV = external global i32 ; <i32*> [#uses=2]
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define void @t1(i32* nocapture %vals, i32 %c) nounwind {
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entry:
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; CHECK: t1:
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; CHECK: cbz
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%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb.nph
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bb.nph: ; preds = %entry
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; CHECK: BB#1
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; CHECK: ldr.n r2, LCPI0_0
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; CHECK: ldr r2, [r2]
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; CHECK: ldr r3, [r2]
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; CHECK: LBB0_2
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; CHECK: LCPI0_0:
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; CHECK-NOT: LCPI0_1:
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; PIC: BB#1
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; PIC: ldr.n r2, LCPI0_0
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; PIC: add r2, pc
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; PIC: ldr r2, [r2]
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; PIC: ldr r3, [r2]
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; PIC: LBB0_2
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; PIC: LCPI0_0:
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; PIC-NOT: LCPI0_1:
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; PIC: .section
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%.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
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br label %bb
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bb: ; preds = %bb, %bb.nph
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%1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; <i32> [#uses=1]
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%i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; <i32> [#uses=2]
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%scevgep = getelementptr i32* %vals, i32 %i.03 ; <i32*> [#uses=1]
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%2 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
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%3 = add nsw i32 %1, %2 ; <i32> [#uses=2]
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store i32 %3, i32* @GV, align 4
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%4 = add i32 %i.03, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %4, %c ; <i1> [#uses=1]
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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; rdar://8001136
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define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
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entry:
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; CHECK: t2:
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; CHECK: adr r{{.}}, #LCPI1_0
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; CHECK: vldmia r3, {d0, d1}
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br i1 undef, label %bb1, label %bb2
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bb1:
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; CHECK-NEXT: %bb1
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%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
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%tmp1 = shl i32 %indvar, 2
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%gep1 = getelementptr i8* %ptr1, i32 %tmp1
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%tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1)
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%tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
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%gep2 = getelementptr i8* %ptr2, i32 %tmp1
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call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1)
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%indvar.next = add i32 %indvar, 1
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%cond = icmp eq i32 %indvar.next, 10
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br i1 %cond, label %bb2, label %bb1
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bb2:
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ret void
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}
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; CHECK: LCPI1_0:
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; CHECK: .section
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declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
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