llvm-6502/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
Bill Wendling 93888428d4 Allow a GR64 to be moved into an MMX register via the "movd" instruction.
Still need to have JIT generate this code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37863 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-04 00:19:54 +00:00

21 lines
860 B
LLVM

; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rsi, %mm0} &&
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {movd %rdi, %mm1} &&
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+mmx | grep {paddusw %mm0, %mm1}
@R = external global <1 x i64> ; <<1 x i64>*> [#uses=1]
define void @foo(<1 x i64> %A, <1 x i64> %B) {
entry:
%tmp4 = bitcast <1 x i64> %B to <4 x i16> ; <<4 x i16>> [#uses=1]
%tmp6 = bitcast <1 x i64> %A to <4 x i16> ; <<4 x i16>> [#uses=1]
%tmp7 = tail call <4 x i16> @llvm.x86.mmx.paddus.w( <4 x i16> %tmp6, <4 x i16> %tmp4 ) ; <<4 x i16>> [#uses=1]
%tmp8 = bitcast <4 x i16> %tmp7 to <1 x i64> ; <<1 x i64>> [#uses=1]
store <1 x i64> %tmp8, <1 x i64>* @R
tail call void @llvm.x86.mmx.emms( )
ret void
}
declare <4 x i16> @llvm.x86.mmx.paddus.w(<4 x i16>, <4 x i16>)
declare void @llvm.x86.mmx.emms()