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e1fee48cd0
used by Clang. To help Clang integration, the PTX target has been split
into two targets: ptx32 and ptx64, depending on the desired pointer size.
- Add GCCBuiltin class to all intrinsics
- Split PTX target into ptx32 and ptx64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129851 91177308-0d34-0410-b5e6-96231b3b80d8
93 lines
4.3 KiB
TableGen
93 lines
4.3 KiB
TableGen
//===- IntrinsicsPTX.td - Defines PTX intrinsics -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the PTX-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "ptx" in {
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multiclass PTXReadSpecialRegisterIntrinsic_v4i32<string prefix> {
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// FIXME: Do we need the 128-bit integer type version?
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// def _r64 : Intrinsic<[llvm_i128_ty], [], [IntrNoMem]>;
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// FIXME: Enable this once v4i32 support is enabled in back-end.
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// def _v4i16 : Intrinsic<[llvm_v4i32_ty], [], [IntrNoMem]>;
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def _x : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<!strconcat(prefix, "_x")>;
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def _y : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<!strconcat(prefix, "_y")>;
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def _z : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<!strconcat(prefix, "_z")>;
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def _w : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<!strconcat(prefix, "_w")>;
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}
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class PTXReadSpecialRegisterIntrinsic_r32<string name>
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<name>;
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class PTXReadSpecialRegisterIntrinsic_r64<string name>
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: Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>,
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GCCBuiltin<name>;
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}
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defm int_ptx_read_tid : PTXReadSpecialRegisterIntrinsic_v4i32
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<"__builtin_ptx_read_tid">;
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defm int_ptx_read_ntid : PTXReadSpecialRegisterIntrinsic_v4i32
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<"__builtin_ptx_read_ntid">;
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def int_ptx_read_laneid : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_laneid">;
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def int_ptx_read_warpid : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_warpid">;
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def int_ptx_read_nwarpid : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_nwarpid">;
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defm int_ptx_read_ctaid : PTXReadSpecialRegisterIntrinsic_v4i32
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<"__builtin_ptx_read_ctaid">;
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defm int_ptx_read_nctaid : PTXReadSpecialRegisterIntrinsic_v4i32
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<"__builtin_ptx_read_nctaid">;
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def int_ptx_read_smid : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_smid">;
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def int_ptx_read_nsmid : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_nsmid">;
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def int_ptx_read_gridid : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_gridid">;
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def int_ptx_read_lanemask_eq : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_lanemask_eq">;
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def int_ptx_read_lanemask_le : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_lanemask_le">;
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def int_ptx_read_lanemask_lt : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_lanemask_lt">;
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def int_ptx_read_lanemask_ge : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_lanemask_ge">;
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def int_ptx_read_lanemask_gt : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_lanemask_gt">;
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def int_ptx_read_clock : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_clock">;
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def int_ptx_read_clock64 : PTXReadSpecialRegisterIntrinsic_r64
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<"__builtin_ptx_read_clock64">;
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def int_ptx_read_pm0 : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_pm0">;
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def int_ptx_read_pm1 : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_pm1">;
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def int_ptx_read_pm2 : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_pm2">;
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def int_ptx_read_pm3 : PTXReadSpecialRegisterIntrinsic_r32
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<"__builtin_ptx_read_pm3">;
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let TargetPrefix = "ptx" in
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def int_ptx_bar_sync : Intrinsic<[], [llvm_i32_ty], []>,
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GCCBuiltin<"__builtin_ptx_bar_sync">;
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