mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
533297b58d
bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
1156 lines
51 KiB
TableGen
1156 lines
51 KiB
TableGen
//===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the SystemZ instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SystemZ Instruction Predicate Definitions.
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def IsZ10 : Predicate<"Subtarget.isZ10()">;
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include "SystemZInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Type Constraints.
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//===----------------------------------------------------------------------===//
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class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
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class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
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class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
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//===----------------------------------------------------------------------===//
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// Type Profiles.
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//===----------------------------------------------------------------------===//
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def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
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def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
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def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_BrCond : SDTypeProfile<0, 3,
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[SDTCisVT<0, OtherVT>,
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SDTCisI8<1>, SDTCisVT<2, i64>]>;
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def SDT_SelectCC : SDTypeProfile<1, 4,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
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SDTCisI8<3>, SDTCisVT<4, i64>]>;
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def SDT_Address : SDTypeProfile<1, 1,
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[SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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//===----------------------------------------------------------------------===//
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// SystemZ Specific Node Definitions.
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//===----------------------------------------------------------------------===//
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def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
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[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
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def SystemZcallseq_start :
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SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
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[SDNPHasChain, SDNPOutFlag]>;
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def SystemZcallseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest>;
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def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest>;
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def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
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[SDNPHasChain]>;
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def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC>;
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def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
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include "SystemZOperands.td"
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//===----------------------------------------------------------------------===//
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// Instruction list..
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
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"#ADJCALLSTACKDOWN",
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[(SystemZcallseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
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"#ADJCALLSTACKUP",
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[(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
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let Uses = [PSW], usesCustomInserter = 1 in {
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def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
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"# Select32 PSEUDO",
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[(set GR32:$dst,
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(SystemZselect GR32:$src1, GR32:$src2, imm:$cc, PSW))]>;
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def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
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"# Select64 PSEUDO",
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[(set GR64:$dst,
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(SystemZselect GR64:$src1, GR64:$src2, imm:$cc, PSW))]>;
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}
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions...
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//
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
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def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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let isBarrier = 1 in {
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def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
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let isIndirectBranch = 1 in
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def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
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}
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let Uses = [PSW] in {
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def JO : Pseudo<(outs), (ins brtarget:$dst),
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"jo\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_O, PSW)]>;
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def JH : Pseudo<(outs), (ins brtarget:$dst),
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"jh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_H, PSW)]>;
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def JNLE: Pseudo<(outs), (ins brtarget:$dst),
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"jnle\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE, PSW)]>;
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def JL : Pseudo<(outs), (ins brtarget:$dst),
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"jl\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_L, PSW)]>;
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def JNHE: Pseudo<(outs), (ins brtarget:$dst),
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"jnhe\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE, PSW)]>;
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def JLH : Pseudo<(outs), (ins brtarget:$dst),
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"jlh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH, PSW)]>;
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def JNE : Pseudo<(outs), (ins brtarget:$dst),
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"jne\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE, PSW)]>;
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def JE : Pseudo<(outs), (ins brtarget:$dst),
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"je\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_E, PSW)]>;
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def JNLH: Pseudo<(outs), (ins brtarget:$dst),
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"jnlh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH, PSW)]>;
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def JHE : Pseudo<(outs), (ins brtarget:$dst),
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"jhe\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE, PSW)]>;
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def JNL : Pseudo<(outs), (ins brtarget:$dst),
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"jnl\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL, PSW)]>;
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def JLE : Pseudo<(outs), (ins brtarget:$dst),
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"jle\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE, PSW)]>;
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def JNH : Pseudo<(outs), (ins brtarget:$dst),
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"jnh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH, PSW)]>;
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def JNO : Pseudo<(outs), (ins brtarget:$dst),
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"jno\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO, PSW)]>;
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} // Uses = [PSW]
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} // isBranch = 1
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. Uses for argument
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// registers are added manually.
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let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
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F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in {
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def CALLi : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
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"brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
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def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
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"basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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//
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let isReMaterializable = 1 in
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// FIXME: Provide imm12 variant
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// FIXME: Address should be halfword aligned...
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def LA64r : RXI<0x47,
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(outs GR64:$dst), (ins laaddr:$src),
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"lay\t{$dst, $src}",
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[(set GR64:$dst, laaddr:$src)]>;
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def LA64rm : RXYI<0x71E3,
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(outs GR64:$dst), (ins i64imm:$src),
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"larl\t{$dst, $src}",
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[(set GR64:$dst,
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(SystemZpcrelwrapper tglobaladdr:$src))]>;
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let neverHasSideEffects = 1 in
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def NOP : Pseudo<(outs), (ins), "# no-op", []>;
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//===----------------------------------------------------------------------===//
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// Move Instructions
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let neverHasSideEffects = 1 in {
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def MOV32rr : RRI<0x18,
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(outs GR32:$dst), (ins GR32:$src),
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"lr\t{$dst, $src}",
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[]>;
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def MOV64rr : RREI<0xB904,
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(outs GR64:$dst), (ins GR64:$src),
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"lgr\t{$dst, $src}",
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[]>;
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def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
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"# MOV128 PSEUDO!\n"
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"\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
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"\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
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[]>;
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def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
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"# MOV64P PSEUDO!\n"
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"\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
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"\tlr\t${dst:subreg_even}, ${src:subreg_even}",
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[]>;
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}
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def MOVSX64rr32 : RREI<0xB914,
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(outs GR64:$dst), (ins GR32:$src),
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"lgfr\t{$dst, $src}",
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[(set GR64:$dst, (sext GR32:$src))]>;
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def MOVZX64rr32 : RREI<0xB916,
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(outs GR64:$dst), (ins GR32:$src),
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"llgfr\t{$dst, $src}",
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[(set GR64:$dst, (zext GR32:$src))]>;
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOV32ri16 : RII<0x8A7,
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(outs GR32:$dst), (ins s16imm:$src),
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"lhi\t{$dst, $src}",
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[(set GR32:$dst, immSExt16:$src)]>;
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def MOV64ri16 : RII<0x9A7,
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(outs GR64:$dst), (ins s16imm64:$src),
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"lghi\t{$dst, $src}",
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[(set GR64:$dst, immSExt16:$src)]>;
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def MOV64rill16 : RII<0xFA5,
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(outs GR64:$dst), (ins i64imm:$src),
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"llill\t{$dst, $src}",
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[(set GR64:$dst, i64ll16:$src)]>;
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def MOV64rilh16 : RII<0xEA5,
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(outs GR64:$dst), (ins i64imm:$src),
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"llilh\t{$dst, $src}",
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[(set GR64:$dst, i64lh16:$src)]>;
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def MOV64rihl16 : RII<0xDA5,
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(outs GR64:$dst), (ins i64imm:$src),
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"llihl\t{$dst, $src}",
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[(set GR64:$dst, i64hl16:$src)]>;
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def MOV64rihh16 : RII<0xCA5,
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(outs GR64:$dst), (ins i64imm:$src),
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"llihh\t{$dst, $src}",
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[(set GR64:$dst, i64hh16:$src)]>;
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def MOV64ri32 : RILI<0x1C0,
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(outs GR64:$dst), (ins s32imm64:$src),
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"lgfi\t{$dst, $src}",
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[(set GR64:$dst, immSExt32:$src)]>;
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def MOV64rilo32 : RILI<0xFC0,
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(outs GR64:$dst), (ins i64imm:$src),
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"llilf\t{$dst, $src}",
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[(set GR64:$dst, i64lo32:$src)]>;
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def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins i64imm:$src),
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"llihf\t{$dst, $src}",
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[(set GR64:$dst, i64hi32:$src)]>;
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}
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def MOV32rm : RXI<0x58,
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(outs GR32:$dst), (ins rriaddr12:$src),
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"l\t{$dst, $src}",
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[(set GR32:$dst, (load rriaddr12:$src))]>;
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def MOV32rmy : RXYI<0x58E3,
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(outs GR32:$dst), (ins rriaddr:$src),
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"ly\t{$dst, $src}",
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[(set GR32:$dst, (load rriaddr:$src))]>;
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def MOV64rm : RXYI<0x04E3,
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(outs GR64:$dst), (ins rriaddr:$src),
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"lg\t{$dst, $src}",
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[(set GR64:$dst, (load rriaddr:$src))]>;
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def MOV64Prm : Pseudo<(outs GR64P:$dst), (ins rriaddr12:$src),
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"# MOV64P PSEUDO!\n"
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"\tl\t${dst:subreg_odd}, $src\n"
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"\tl\t${dst:subreg_even}, 4+$src",
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[(set GR64P:$dst, (load rriaddr12:$src))]>;
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def MOV64Prmy : Pseudo<(outs GR64P:$dst), (ins rriaddr:$src),
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"# MOV64P PSEUDO!\n"
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"\tly\t${dst:subreg_odd}, $src\n"
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"\tly\t${dst:subreg_even}, 4+$src",
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[(set GR64P:$dst, (load rriaddr:$src))]>;
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def MOV128rm : Pseudo<(outs GR128:$dst), (ins rriaddr:$src),
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"# MOV128 PSEUDO!\n"
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"\tlg\t${dst:subreg_odd}, $src\n"
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"\tlg\t${dst:subreg_even}, 8+$src",
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[(set GR128:$dst, (load rriaddr:$src))]>;
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}
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def MOV32mr : RXI<0x50,
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(outs), (ins rriaddr12:$dst, GR32:$src),
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"st\t{$src, $dst}",
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[(store GR32:$src, rriaddr12:$dst)]>;
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def MOV32mry : RXYI<0x50E3,
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(outs), (ins rriaddr:$dst, GR32:$src),
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"sty\t{$src, $dst}",
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[(store GR32:$src, rriaddr:$dst)]>;
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def MOV64mr : RXYI<0x24E3,
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(outs), (ins rriaddr:$dst, GR64:$src),
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"stg\t{$src, $dst}",
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[(store GR64:$src, rriaddr:$dst)]>;
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def MOV64Pmr : Pseudo<(outs), (ins rriaddr12:$dst, GR64P:$src),
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"# MOV64P PSEUDO!\n"
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"\tst\t${src:subreg_odd}, $dst\n"
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"\tst\t${src:subreg_even}, 4+$dst",
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[(store GR64P:$src, rriaddr12:$dst)]>;
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def MOV64Pmry : Pseudo<(outs), (ins rriaddr:$dst, GR64P:$src),
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"# MOV64P PSEUDO!\n"
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"\tsty\t${src:subreg_odd}, $dst\n"
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"\tsty\t${src:subreg_even}, 4+$dst",
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[(store GR64P:$src, rriaddr:$dst)]>;
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def MOV128mr : Pseudo<(outs), (ins rriaddr:$dst, GR128:$src),
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"# MOV128 PSEUDO!\n"
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"\tstg\t${src:subreg_odd}, $dst\n"
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"\tstg\t${src:subreg_even}, 8+$dst",
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[(store GR128:$src, rriaddr:$dst)]>;
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def MOV8mi : SII<0x92,
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(outs), (ins riaddr12:$dst, i32i8imm:$src),
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"mvi\t{$dst, $src}",
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[(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
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def MOV8miy : SIYI<0x52EB,
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(outs), (ins riaddr:$dst, i32i8imm:$src),
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"mviy\t{$dst, $src}",
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[(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
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let AddedComplexity = 2 in {
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def MOV16mi : SILI<0xE544,
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(outs), (ins riaddr12:$dst, s16imm:$src),
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"mvhhi\t{$dst, $src}",
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[(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
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Requires<[IsZ10]>;
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def MOV32mi16 : SILI<0xE54C,
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(outs), (ins riaddr12:$dst, s32imm:$src),
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"mvhi\t{$dst, $src}",
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[(store (i32 immSExt16:$src), riaddr12:$dst)]>,
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Requires<[IsZ10]>;
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def MOV64mi16 : SILI<0xE548,
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(outs), (ins riaddr12:$dst, s32imm64:$src),
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"mvghi\t{$dst, $src}",
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[(store (i64 immSExt16:$src), riaddr12:$dst)]>,
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Requires<[IsZ10]>;
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}
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// sexts
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def MOVSX32rr8 : RREI<0xB926,
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(outs GR32:$dst), (ins GR32:$src),
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"lbr\t{$dst, $src}",
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[(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
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def MOVSX64rr8 : RREI<0xB906,
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(outs GR64:$dst), (ins GR64:$src),
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"lgbr\t{$dst, $src}",
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[(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
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def MOVSX32rr16 : RREI<0xB927,
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(outs GR32:$dst), (ins GR32:$src),
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"lhr\t{$dst, $src}",
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[(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
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def MOVSX64rr16 : RREI<0xB907,
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(outs GR64:$dst), (ins GR64:$src),
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"lghr\t{$dst, $src}",
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[(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
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// extloads
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def MOVSX32rm8 : RXYI<0x76E3,
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(outs GR32:$dst), (ins rriaddr:$src),
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"lb\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
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def MOVSX32rm16 : RXI<0x48,
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(outs GR32:$dst), (ins rriaddr12:$src),
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"lh\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
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def MOVSX32rm16y : RXYI<0x78E3,
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(outs GR32:$dst), (ins rriaddr:$src),
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"lhy\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
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def MOVSX64rm8 : RXYI<0x77E3,
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(outs GR64:$dst), (ins rriaddr:$src),
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"lgb\t{$dst, $src}",
|
|
[(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
|
|
def MOVSX64rm16 : RXYI<0x15E3,
|
|
(outs GR64:$dst), (ins rriaddr:$src),
|
|
"lgh\t{$dst, $src}",
|
|
[(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
|
|
def MOVSX64rm32 : RXYI<0x14E3,
|
|
(outs GR64:$dst), (ins rriaddr:$src),
|
|
"lgf\t{$dst, $src}",
|
|
[(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
|
|
|
|
def MOVZX32rm8 : RXYI<0x94E3,
|
|
(outs GR32:$dst), (ins rriaddr:$src),
|
|
"llc\t{$dst, $src}",
|
|
[(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
|
|
def MOVZX32rm16 : RXYI<0x95E3,
|
|
(outs GR32:$dst), (ins rriaddr:$src),
|
|
"llh\t{$dst, $src}",
|
|
[(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
|
|
def MOVZX64rm8 : RXYI<0x90E3,
|
|
(outs GR64:$dst), (ins rriaddr:$src),
|
|
"llgc\t{$dst, $src}",
|
|
[(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
|
|
def MOVZX64rm16 : RXYI<0x91E3,
|
|
(outs GR64:$dst), (ins rriaddr:$src),
|
|
"llgh\t{$dst, $src}",
|
|
[(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
|
|
def MOVZX64rm32 : RXYI<0x16E3,
|
|
(outs GR64:$dst), (ins rriaddr:$src),
|
|
"llgf\t{$dst, $src}",
|
|
[(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
|
|
|
|
// truncstores
|
|
def MOV32m8r : RXI<0x42,
|
|
(outs), (ins rriaddr12:$dst, GR32:$src),
|
|
"stc\t{$src, $dst}",
|
|
[(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
|
|
|
|
def MOV32m8ry : RXYI<0x72E3,
|
|
(outs), (ins rriaddr:$dst, GR32:$src),
|
|
"stcy\t{$src, $dst}",
|
|
[(truncstorei8 GR32:$src, rriaddr:$dst)]>;
|
|
|
|
def MOV32m16r : RXI<0x40,
|
|
(outs), (ins rriaddr12:$dst, GR32:$src),
|
|
"sth\t{$src, $dst}",
|
|
[(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
|
|
|
|
def MOV32m16ry : RXYI<0x70E3,
|
|
(outs), (ins rriaddr:$dst, GR32:$src),
|
|
"sthy\t{$src, $dst}",
|
|
[(truncstorei16 GR32:$src, rriaddr:$dst)]>;
|
|
|
|
def MOV64m8r : RXI<0x42,
|
|
(outs), (ins rriaddr12:$dst, GR64:$src),
|
|
"stc\t{$src, $dst}",
|
|
[(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
|
|
|
|
def MOV64m8ry : RXYI<0x72E3,
|
|
(outs), (ins rriaddr:$dst, GR64:$src),
|
|
"stcy\t{$src, $dst}",
|
|
[(truncstorei8 GR64:$src, rriaddr:$dst)]>;
|
|
|
|
def MOV64m16r : RXI<0x40,
|
|
(outs), (ins rriaddr12:$dst, GR64:$src),
|
|
"sth\t{$src, $dst}",
|
|
[(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
|
|
|
|
def MOV64m16ry : RXYI<0x70E3,
|
|
(outs), (ins rriaddr:$dst, GR64:$src),
|
|
"sthy\t{$src, $dst}",
|
|
[(truncstorei16 GR64:$src, rriaddr:$dst)]>;
|
|
|
|
def MOV64m32r : RXI<0x50,
|
|
(outs), (ins rriaddr12:$dst, GR64:$src),
|
|
"st\t{$src, $dst}",
|
|
[(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
|
|
|
|
def MOV64m32ry : RXYI<0x50E3,
|
|
(outs), (ins rriaddr:$dst, GR64:$src),
|
|
"sty\t{$src, $dst}",
|
|
[(truncstorei32 GR64:$src, rriaddr:$dst)]>;
|
|
|
|
// multiple regs moves
|
|
// FIXME: should we use multiple arg nodes?
|
|
def MOV32mrm : RSYI<0x90EB,
|
|
(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
|
|
"stmy\t{$from, $to, $dst}",
|
|
[]>;
|
|
def MOV64mrm : RSYI<0x24EB,
|
|
(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
|
|
"stmg\t{$from, $to, $dst}",
|
|
[]>;
|
|
def MOV32rmm : RSYI<0x90EB,
|
|
(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
|
|
"lmy\t{$from, $to, $dst}",
|
|
[]>;
|
|
def MOV64rmm : RSYI<0x04EB,
|
|
(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
|
|
"lmg\t{$from, $to, $dst}",
|
|
[]>;
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
|
|
def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
|
|
"lhi\t${dst:subreg_even}, 0",
|
|
[]>;
|
|
def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
|
|
"lghi\t${dst:subreg_even}, 0",
|
|
[]>;
|
|
}
|
|
|
|
// Byte swaps
|
|
def BSWAP32rr : RREI<0xB91F,
|
|
(outs GR32:$dst), (ins GR32:$src),
|
|
"lrvr\t{$dst, $src}",
|
|
[(set GR32:$dst, (bswap GR32:$src))]>;
|
|
def BSWAP64rr : RREI<0xB90F,
|
|
(outs GR64:$dst), (ins GR64:$src),
|
|
"lrvgr\t{$dst, $src}",
|
|
[(set GR64:$dst, (bswap GR64:$src))]>;
|
|
|
|
// FIXME: this is invalid pattern for big-endian
|
|
//def BSWAP16rm : RXYI<0x1FE3, (outs GR32:$dst), (ins rriaddr:$src),
|
|
// "lrvh\t{$dst, $src}",
|
|
// [(set GR32:$dst, (bswap (extloadi32i16 rriaddr:$src)))]>;
|
|
def BSWAP32rm : RXYI<0x1EE3, (outs GR32:$dst), (ins rriaddr:$src),
|
|
"lrv\t{$dst, $src}",
|
|
[(set GR32:$dst, (bswap (load rriaddr:$src)))]>;
|
|
def BSWAP64rm : RXYI<0x0FE3, (outs GR64:$dst), (ins rriaddr:$src),
|
|
"lrvg\t{$dst, $src}",
|
|
[(set GR64:$dst, (bswap (load rriaddr:$src)))]>;
|
|
|
|
//def BSWAP16mr : RXYI<0xE33F, (outs), (ins rriaddr:$dst, GR32:$src),
|
|
// "strvh\t{$src, $dst}",
|
|
// [(truncstorei16 (bswap GR32:$src), rriaddr:$dst)]>;
|
|
def BSWAP32mr : RXYI<0xE33E, (outs), (ins rriaddr:$dst, GR32:$src),
|
|
"strv\t{$src, $dst}",
|
|
[(store (bswap GR32:$src), rriaddr:$dst)]>;
|
|
def BSWAP64mr : RXYI<0xE32F, (outs), (ins rriaddr:$dst, GR64:$src),
|
|
"strvg\t{$src, $dst}",
|
|
[(store (bswap GR64:$src), rriaddr:$dst)]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arithmetic Instructions
|
|
|
|
let Defs = [PSW] in {
|
|
def NEG32rr : RRI<0x13,
|
|
(outs GR32:$dst), (ins GR32:$src),
|
|
"lcr\t{$dst, $src}",
|
|
[(set GR32:$dst, (ineg GR32:$src)),
|
|
(implicit PSW)]>;
|
|
def NEG64rr : RREI<0xB903, (outs GR64:$dst), (ins GR64:$src),
|
|
"lcgr\t{$dst, $src}",
|
|
[(set GR64:$dst, (ineg GR64:$src)),
|
|
(implicit PSW)]>;
|
|
def NEG64rr32 : RREI<0xB913, (outs GR64:$dst), (ins GR32:$src),
|
|
"lcgfr\t{$dst, $src}",
|
|
[(set GR64:$dst, (ineg (sext GR32:$src))),
|
|
(implicit PSW)]>;
|
|
}
|
|
|
|
let isTwoAddress = 1 in {
|
|
|
|
let Defs = [PSW] in {
|
|
|
|
let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
|
|
def ADD32rr : RRI<0x1A, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"ar\t{$dst, $src2}",
|
|
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
|
|
(implicit PSW)]>;
|
|
def ADD64rr : RREI<0xB908, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"agr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
|
|
(implicit PSW)]>;
|
|
}
|
|
|
|
def ADD32rm : RXI<0x5A, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
|
|
"a\t{$dst, $src2}",
|
|
[(set GR32:$dst, (add GR32:$src1, (load rriaddr12:$src2))),
|
|
(implicit PSW)]>;
|
|
def ADD32rmy : RXYI<0xE35A, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
|
"ay\t{$dst, $src2}",
|
|
[(set GR32:$dst, (add GR32:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
def ADD64rm : RXYI<0xE308, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
|
"ag\t{$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
|
|
|
|
def ADD32ri16 : RII<0xA7A,
|
|
(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
|
|
"ahi\t{$dst, $src2}",
|
|
[(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
|
|
(implicit PSW)]>;
|
|
def ADD32ri : RILI<0xC29,
|
|
(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
|
|
"afi\t{$dst, $src2}",
|
|
[(set GR32:$dst, (add GR32:$src1, imm:$src2)),
|
|
(implicit PSW)]>;
|
|
def ADD64ri16 : RILI<0xA7B,
|
|
(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
|
|
"aghi\t{$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
|
|
(implicit PSW)]>;
|
|
def ADD64ri32 : RILI<0xC28,
|
|
(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
|
|
"agfi\t{$dst, $src2}",
|
|
[(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
|
|
(implicit PSW)]>;
|
|
|
|
let isCommutable = 1 in { // X = ADC Y, Z == X = ADC Z, Y
|
|
def ADC32rr : RRI<0x1E, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"alr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (addc GR32:$src1, GR32:$src2))]>;
|
|
def ADC64rr : RREI<0xB90A, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"algr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (addc GR64:$src1, GR64:$src2))]>;
|
|
}
|
|
|
|
def ADC32ri : RILI<0xC2B,
|
|
(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
|
|
"alfi\t{$dst, $src2}",
|
|
[(set GR32:$dst, (addc GR32:$src1, imm:$src2))]>;
|
|
def ADC64ri32 : RILI<0xC2A,
|
|
(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
|
|
"algfi\t{$dst, $src2}",
|
|
[(set GR64:$dst, (addc GR64:$src1, immSExt32:$src2))]>;
|
|
|
|
let Uses = [PSW] in {
|
|
def ADDE32rr : RREI<0xB998, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"alcr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (adde GR32:$src1, GR32:$src2)),
|
|
(implicit PSW)]>;
|
|
def ADDE64rr : RREI<0xB988, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"alcgr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (adde GR64:$src1, GR64:$src2)),
|
|
(implicit PSW)]>;
|
|
}
|
|
|
|
let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
|
|
def AND32rr : RRI<0x14,
|
|
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"nr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
|
|
def AND64rr : RREI<0xB980,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"ngr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
|
|
}
|
|
|
|
def AND32rm : RXI<0x54, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
|
|
"n\t{$dst, $src2}",
|
|
[(set GR32:$dst, (and GR32:$src1, (load rriaddr12:$src2))),
|
|
(implicit PSW)]>;
|
|
def AND32rmy : RXYI<0xE354, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
|
"ny\t{$dst, $src2}",
|
|
[(set GR32:$dst, (and GR32:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
def AND64rm : RXYI<0xE360, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
|
"ng\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
|
|
def AND32rill16 : RII<0xA57,
|
|
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|
"nill\t{$dst, $src2}",
|
|
[(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
|
|
def AND64rill16 : RII<0xA57,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"nill\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
|
|
|
|
def AND32rilh16 : RII<0xA56,
|
|
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|
"nilh\t{$dst, $src2}",
|
|
[(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
|
|
def AND64rilh16 : RII<0xA56,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"nilh\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
|
|
|
|
def AND64rihl16 : RII<0xA55,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"nihl\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
|
|
def AND64rihh16 : RII<0xA54,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"nihh\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
|
|
|
|
def AND32ri : RILI<0xC0B,
|
|
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|
"nilf\t{$dst, $src2}",
|
|
[(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
|
|
def AND64rilo32 : RILI<0xC0B,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"nilf\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
|
|
def AND64rihi32 : RILI<0xC0A,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"nihf\t{$dst, $src2}",
|
|
[(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
|
|
|
|
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
|
|
def OR32rr : RRI<0x16,
|
|
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"or\t{$dst, $src2}",
|
|
[(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
|
|
def OR64rr : RREI<0xB981,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"ogr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
|
|
}
|
|
|
|
def OR32rm : RXI<0x56, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
|
|
"o\t{$dst, $src2}",
|
|
[(set GR32:$dst, (or GR32:$src1, (load rriaddr12:$src2))),
|
|
(implicit PSW)]>;
|
|
def OR32rmy : RXYI<0xE356, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
|
"oy\t{$dst, $src2}",
|
|
[(set GR32:$dst, (or GR32:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
def OR64rm : RXYI<0xE381, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
|
"og\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
|
|
// FIXME: Provide proper encoding!
|
|
def OR32ri16 : RII<0xA5B,
|
|
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|
"oill\t{$dst, $src2}",
|
|
[(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
|
|
def OR32ri16h : RII<0xA5A,
|
|
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|
"oilh\t{$dst, $src2}",
|
|
[(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
|
|
def OR32ri : RILI<0xC0D,
|
|
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|
"oilf\t{$dst, $src2}",
|
|
[(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
|
|
|
|
def OR64rill16 : RII<0xA5B,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"oill\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
|
|
def OR64rilh16 : RII<0xA5A,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"oilh\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
|
|
def OR64rihl16 : RII<0xA59,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"oihl\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
|
|
def OR64rihh16 : RII<0xA58,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"oihh\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
|
|
|
|
def OR64rilo32 : RILI<0xC0D,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"oilf\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
|
|
def OR64rihi32 : RILI<0xC0C,
|
|
(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
|
|
"oihf\t{$dst, $src2}",
|
|
[(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
|
|
|
|
def SUB32rr : RRI<0x1B,
|
|
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"sr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
|
|
def SUB64rr : RREI<0xB909,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"sgr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
|
|
|
|
def SUB32rm : RXI<0x5B, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
|
|
"s\t{$dst, $src2}",
|
|
[(set GR32:$dst, (sub GR32:$src1, (load rriaddr12:$src2))),
|
|
(implicit PSW)]>;
|
|
def SUB32rmy : RXYI<0xE35B, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
|
"sy\t{$dst, $src2}",
|
|
[(set GR32:$dst, (sub GR32:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
def SUB64rm : RXYI<0xE309, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
|
"sg\t{$dst, $src2}",
|
|
[(set GR64:$dst, (sub GR64:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
|
|
def SBC32rr : RRI<0x1F,
|
|
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"slr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (subc GR32:$src1, GR32:$src2))]>;
|
|
def SBC64rr : RREI<0xB90B,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"slgr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (subc GR64:$src1, GR64:$src2))]>;
|
|
|
|
def SBC32ri : RILI<0xC25,
|
|
(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
|
|
"sllfi\t{$dst, $src2}",
|
|
[(set GR32:$dst, (subc GR32:$src1, imm:$src2))]>;
|
|
def SBC64ri32 : RILI<0xC24,
|
|
(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
|
|
"slgfi\t{$dst, $src2}",
|
|
[(set GR64:$dst, (subc GR64:$src1, immSExt32:$src2))]>;
|
|
|
|
let Uses = [PSW] in {
|
|
def SUBE32rr : RREI<0xB999, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"slbr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (sube GR32:$src1, GR32:$src2)),
|
|
(implicit PSW)]>;
|
|
def SUBE64rr : RREI<0xB989, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"slbgr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (sube GR64:$src1, GR64:$src2)),
|
|
(implicit PSW)]>;
|
|
}
|
|
|
|
let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
|
|
def XOR32rr : RRI<0x17,
|
|
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"xr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
|
|
def XOR64rr : RREI<0xB982,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"xgr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
|
|
}
|
|
|
|
def XOR32rm : RXI<0x57,(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
|
|
"x\t{$dst, $src2}",
|
|
[(set GR32:$dst, (xor GR32:$src1, (load rriaddr12:$src2))),
|
|
(implicit PSW)]>;
|
|
def XOR32rmy : RXYI<0xE357, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
|
"xy\t{$dst, $src2}",
|
|
[(set GR32:$dst, (xor GR32:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
def XOR64rm : RXYI<0xE382, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
|
"xg\t{$dst, $src2}",
|
|
[(set GR64:$dst, (xor GR64:$src1, (load rriaddr:$src2))),
|
|
(implicit PSW)]>;
|
|
|
|
def XOR32ri : RILI<0xC07,
|
|
(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
|
|
"xilf\t{$dst, $src2}",
|
|
[(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
|
|
|
|
} // Defs = [PSW]
|
|
|
|
let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
|
|
def MUL32rr : RREI<0xB252,
|
|
(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
|
"msr\t{$dst, $src2}",
|
|
[(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
|
|
def MUL64rr : RREI<0xB90C,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
|
"msgr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
|
|
}
|
|
|
|
def MUL64rrP : RRI<0x1C,
|
|
(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
|
|
"mr\t{$dst, $src2}",
|
|
[]>;
|
|
def UMUL64rrP : RREI<0xB996,
|
|
(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
|
|
"mlr\t{$dst, $src2}",
|
|
[]>;
|
|
def UMUL128rrP : RREI<0xB986,
|
|
(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
|
|
"mlgr\t{$dst, $src2}",
|
|
[]>;
|
|
|
|
def MUL32ri16 : RII<0xA7C,
|
|
(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
|
|
"mhi\t{$dst, $src2}",
|
|
[(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
|
|
def MUL64ri16 : RII<0xA7D,
|
|
(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
|
|
"mghi\t{$dst, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
|
|
|
|
let AddedComplexity = 2 in {
|
|
def MUL32ri : RILI<0xC21,
|
|
(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
|
|
"msfi\t{$dst, $src2}",
|
|
[(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
|
|
Requires<[IsZ10]>;
|
|
def MUL64ri32 : RILI<0xC20,
|
|
(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
|
|
"msgfi\t{$dst, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
|
|
Requires<[IsZ10]>;
|
|
}
|
|
|
|
def MUL32rm : RXI<0x71,
|
|
(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
|
|
"ms\t{$dst, $src2}",
|
|
[(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
|
|
def MUL32rmy : RXYI<0xE351,
|
|
(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
|
"msy\t{$dst, $src2}",
|
|
[(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
|
|
def MUL64rm : RXYI<0xE30C,
|
|
(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
|
"msg\t{$dst, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
|
|
|
|
def MULSX64rr32 : RREI<0xB91C,
|
|
(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
|
|
"msgfr\t{$dst, $src2}",
|
|
[(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
|
|
|
|
def SDIVREM32r : RREI<0xB91D,
|
|
(outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
|
|
"dsgfr\t{$dst, $src2}",
|
|
[]>;
|
|
def SDIVREM64r : RREI<0xB90D,
|
|
(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
|
|
"dsgr\t{$dst, $src2}",
|
|
[]>;
|
|
|
|
def UDIVREM32r : RREI<0xB997,
|
|
(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
|
|
"dlr\t{$dst, $src2}",
|
|
[]>;
|
|
def UDIVREM64r : RREI<0xB987,
|
|
(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
|
|
"dlgr\t{$dst, $src2}",
|
|
[]>;
|
|
let mayLoad = 1 in {
|
|
def SDIVREM32m : RXYI<0xE31D,
|
|
(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
|
|
"dsgf\t{$dst, $src2}",
|
|
[]>;
|
|
def SDIVREM64m : RXYI<0xE30D,
|
|
(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
|
|
"dsg\t{$dst, $src2}",
|
|
[]>;
|
|
|
|
def UDIVREM32m : RXYI<0xE397, (outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
|
|
"dl\t{$dst, $src2}",
|
|
[]>;
|
|
def UDIVREM64m : RXYI<0xE387, (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
|
|
"dlg\t{$dst, $src2}",
|
|
[]>;
|
|
} // mayLoad
|
|
} // isTwoAddress = 1
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Shifts
|
|
|
|
let isTwoAddress = 1 in
|
|
def SRL32rri : RSI<0x88,
|
|
(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
|
|
"srl\t{$src, $amt}",
|
|
[(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
|
|
def SRL64rri : RSYI<0xEB0C,
|
|
(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
|
|
"srlg\t{$dst, $src, $amt}",
|
|
[(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
|
|
|
|
let isTwoAddress = 1 in
|
|
def SHL32rri : RSI<0x89,
|
|
(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
|
|
"sll\t{$src, $amt}",
|
|
[(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
|
|
def SHL64rri : RSYI<0xEB0D,
|
|
(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
|
|
"sllg\t{$dst, $src, $amt}",
|
|
[(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
|
|
|
|
let Defs = [PSW] in {
|
|
let isTwoAddress = 1 in
|
|
def SRA32rri : RSI<0x8A,
|
|
(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
|
|
"sra\t{$src, $amt}",
|
|
[(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
|
|
(implicit PSW)]>;
|
|
|
|
def SRA64rri : RSYI<0xEB0A,
|
|
(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
|
|
"srag\t{$dst, $src, $amt}",
|
|
[(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
|
|
(implicit PSW)]>;
|
|
} // Defs = [PSW]
|
|
|
|
def ROTL32rri : RSYI<0xEB1D,
|
|
(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
|
|
"rll\t{$dst, $src, $amt}",
|
|
[(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
|
|
def ROTL64rri : RSYI<0xEB1C,
|
|
(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
|
|
"rllg\t{$dst, $src, $amt}",
|
|
[(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Test instructions (like AND but do not produce any result)
|
|
|
|
// Integer comparisons
|
|
let Defs = [PSW] in {
|
|
def CMP32rr : RRI<0x19,
|
|
(outs), (ins GR32:$src1, GR32:$src2),
|
|
"cr\t$src1, $src2",
|
|
[(SystemZcmp GR32:$src1, GR32:$src2),
|
|
(implicit PSW)]>;
|
|
def CMP64rr : RREI<0xB920,
|
|
(outs), (ins GR64:$src1, GR64:$src2),
|
|
"cgr\t$src1, $src2",
|
|
[(SystemZcmp GR64:$src1, GR64:$src2),
|
|
(implicit PSW)]>;
|
|
|
|
def CMP32ri : RILI<0xC2D,
|
|
(outs), (ins GR32:$src1, s32imm:$src2),
|
|
"cfi\t$src1, $src2",
|
|
[(SystemZcmp GR32:$src1, imm:$src2),
|
|
(implicit PSW)]>;
|
|
def CMP64ri32 : RILI<0xC2C,
|
|
(outs), (ins GR64:$src1, s32imm64:$src2),
|
|
"cgfi\t$src1, $src2",
|
|
[(SystemZcmp GR64:$src1, i64immSExt32:$src2),
|
|
(implicit PSW)]>;
|
|
|
|
def CMP32rm : RXI<0x59,
|
|
(outs), (ins GR32:$src1, rriaddr12:$src2),
|
|
"c\t$src1, $src2",
|
|
[(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
|
|
(implicit PSW)]>;
|
|
def CMP32rmy : RXYI<0xE359,
|
|
(outs), (ins GR32:$src1, rriaddr:$src2),
|
|
"cy\t$src1, $src2",
|
|
[(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
|
|
(implicit PSW)]>;
|
|
def CMP64rm : RXYI<0xE320,
|
|
(outs), (ins GR64:$src1, rriaddr:$src2),
|
|
"cg\t$src1, $src2",
|
|
[(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
|
|
(implicit PSW)]>;
|
|
|
|
def UCMP32rr : RRI<0x15,
|
|
(outs), (ins GR32:$src1, GR32:$src2),
|
|
"clr\t$src1, $src2",
|
|
[(SystemZucmp GR32:$src1, GR32:$src2),
|
|
(implicit PSW)]>;
|
|
def UCMP64rr : RREI<0xB921,
|
|
(outs), (ins GR64:$src1, GR64:$src2),
|
|
"clgr\t$src1, $src2",
|
|
[(SystemZucmp GR64:$src1, GR64:$src2),
|
|
(implicit PSW)]>;
|
|
|
|
def UCMP32ri : RILI<0xC2F,
|
|
(outs), (ins GR32:$src1, i32imm:$src2),
|
|
"clfi\t$src1, $src2",
|
|
[(SystemZucmp GR32:$src1, imm:$src2),
|
|
(implicit PSW)]>;
|
|
def UCMP64ri32 : RILI<0xC2E,
|
|
(outs), (ins GR64:$src1, i64i32imm:$src2),
|
|
"clgfi\t$src1, $src2",
|
|
[(SystemZucmp GR64:$src1, i64immZExt32:$src2),
|
|
(implicit PSW)]>;
|
|
|
|
def UCMP32rm : RXI<0x55,
|
|
(outs), (ins GR32:$src1, rriaddr12:$src2),
|
|
"cl\t$src1, $src2",
|
|
[(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
|
|
(implicit PSW)]>;
|
|
def UCMP32rmy : RXYI<0xE355,
|
|
(outs), (ins GR32:$src1, rriaddr:$src2),
|
|
"cly\t$src1, $src2",
|
|
[(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
|
|
(implicit PSW)]>;
|
|
def UCMP64rm : RXYI<0xE351,
|
|
(outs), (ins GR64:$src1, rriaddr:$src2),
|
|
"clg\t$src1, $src2",
|
|
[(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
|
|
(implicit PSW)]>;
|
|
|
|
def CMPSX64rr32 : RREI<0xB930,
|
|
(outs), (ins GR64:$src1, GR32:$src2),
|
|
"cgfr\t$src1, $src2",
|
|
[(SystemZucmp GR64:$src1, (sext GR32:$src2)),
|
|
(implicit PSW)]>;
|
|
def UCMPZX64rr32 : RREI<0xB931,
|
|
(outs), (ins GR64:$src1, GR32:$src2),
|
|
"clgfr\t$src1, $src2",
|
|
[(SystemZucmp GR64:$src1, (zext GR32:$src2)),
|
|
(implicit PSW)]>;
|
|
|
|
def CMPSX64rm32 : RXYI<0xE330,
|
|
(outs), (ins GR64:$src1, rriaddr:$src2),
|
|
"cgf\t$src1, $src2",
|
|
[(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
|
|
(implicit PSW)]>;
|
|
def UCMPZX64rm32 : RXYI<0xE331,
|
|
(outs), (ins GR64:$src1, rriaddr:$src2),
|
|
"clgf\t$src1, $src2",
|
|
[(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
|
|
(implicit PSW)]>;
|
|
|
|
// FIXME: Add other crazy ucmp forms
|
|
|
|
} // Defs = [PSW]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Other crazy stuff
|
|
let Defs = [PSW] in {
|
|
def FLOGR64 : RREI<0xB983,
|
|
(outs GR128:$dst), (ins GR64:$src),
|
|
"flogr\t{$dst, $src}",
|
|
[]>;
|
|
} // Defs = [PSW]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// ConstPools, JumpTables
|
|
def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
|
|
def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>;
|
|
|
|
// anyext
|
|
def : Pat<(i64 (anyext GR32:$src)),
|
|
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
|
|
|
|
// calls
|
|
def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
|
|
def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Peepholes.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// FIXME: use add/sub tricks with 32678/-32768
|
|
|
|
// Arbitrary immediate support.
|
|
def : Pat<(i32 imm:$src),
|
|
(EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
|
|
|
|
// Implement in terms of LLIHF/OILF.
|
|
def : Pat<(i64 imm:$imm),
|
|
(OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
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// trunc patterns
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def : Pat<(i32 (trunc GR64:$src)),
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(EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
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// sext_inreg patterns
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def : Pat<(sext_inreg GR64:$src, i32),
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(MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
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// extload patterns
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def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>;
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def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
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def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>;
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def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
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def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
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// muls
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def : Pat<(mulhs GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd32),
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GR32:$src2),
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subreg_even32)>;
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def : Pat<(mulhu GR32:$src1, GR32:$src2),
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(EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
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GR32:$src1, subreg_odd32),
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GR32:$src2),
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subreg_even32)>;
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def : Pat<(mulhu GR64:$src1, GR64:$src2),
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(EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_even)>;
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def : Pat<(ctlz GR64:$src),
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(EXTRACT_SUBREG (FLOGR64 GR64:$src), subreg_even)>;
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