mirror of
https://github.com/c64scene-ar/llvm-6502.git
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74a2151392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95410 91177308-0d34-0410-b5e6-96231b3b80d8
465 lines
15 KiB
C++
465 lines
15 KiB
C++
//===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86MCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86-emitter"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class X86MCCodeEmitter : public MCCodeEmitter {
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X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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bool Is64BitMode;
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public:
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X86MCCodeEmitter(TargetMachine &tm)
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: TM(tm), TII(*TM.getInstrInfo()) {
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// FIXME: Get this from the right place.
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Is64BitMode = false;
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}
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~X86MCCodeEmitter() {}
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static unsigned GetX86RegNum(const MCOperand &MO) {
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return X86RegisterInfo::getX86RegNum(MO.getReg());
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}
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void EmitByte(unsigned char C, raw_ostream &OS) const {
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OS << (char)C;
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}
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void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, OS);
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Val >>= 8;
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}
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}
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void EmitDisplacementField(const MCOperand *RelocOp, int DispVal,
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int64_t Adj, bool IsPCRel, raw_ostream &OS) const;
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
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raw_ostream &OS) const {
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EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), OS);
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}
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void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
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raw_ostream &OS) const {
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// SIB byte is in the same format as the ModRMByte...
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EmitByte(ModRMByte(SS, Index, Base), OS);
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}
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void EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField, intptr_t PCAdj,
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raw_ostream &OS) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
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TargetMachine &TM) {
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return new X86MCCodeEmitter(TM);
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}
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/// isDisp8 - Return true if this signed displacement fits in a 8-bit
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/// sign-extended field.
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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void X86MCCodeEmitter::
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EmitDisplacementField(const MCOperand *RelocOp, int DispVal,
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int64_t Adj, bool IsPCRel, raw_ostream &OS) const {
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// If this is a simple integer displacement that doesn't require a relocation,
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// emit it now.
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if (!RelocOp) {
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EmitConstant(DispVal, 4, OS);
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return;
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}
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assert(0 && "Reloc not handled yet");
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#if 0
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// Otherwise, this is something that requires a relocation. Emit it as such
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// now.
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unsigned RelocType = Is64BitMode ?
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(IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
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: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
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if (RelocOp->isGlobal()) {
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// In 64-bit static small code model, we could potentially emit absolute.
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// But it's probably not beneficial. If the MCE supports using RIP directly
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// do it, otherwise fallback to absolute (this is determined by IsPCRel).
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// 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
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// 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
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bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
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emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
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Adj, Indirect);
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} else if (RelocOp->isSymbol()) {
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emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
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} else if (RelocOp->isCPI()) {
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emitConstPoolAddress(RelocOp->getIndex(), RelocType,
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RelocOp->getOffset(), Adj);
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} else {
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assert(RelocOp->isJTI() && "Unexpected machine operand!");
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emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
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}
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#endif
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}
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void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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intptr_t PCAdj,
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raw_ostream &OS) const {
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const MCOperand &Op3 = MI.getOperand(Op+3);
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int DispVal = 0;
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const MCOperand *DispForReloc = 0;
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// Figure out what sort of displacement we have to handle here.
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if (Op3.isImm()) {
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DispVal = Op3.getImm();
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} else {
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assert(0 && "relocatable operand");
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#if 0
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if (Op3.isGlobal()) {
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DispForReloc = &Op3;
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} else if (Op3.isSymbol()) {
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DispForReloc = &Op3;
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} else if (Op3.isCPI()) {
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if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
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DispVal += Op3.getOffset();
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}
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} else {
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assert(Op3.isJTI());
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if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
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}
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#endif
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}
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const MCOperand &Base = MI.getOperand(Op);
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const MCOperand &Scale = MI.getOperand(Op+1);
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const MCOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = Base.getReg();
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// FIXME: Eliminate!
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bool IsPCRel = false;
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// Is a SIB byte needed?
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// If no BaseReg, issue a RIP relative instruction only if the MCE can
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// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
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// 2-7) and absolute references.
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if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
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IndexReg.getReg() == 0 &&
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(BaseReg == X86::RIP || (BaseReg != 0 && BaseReg != X86::ESP))) {
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if (BaseReg == 0 || BaseReg == X86::RIP) { // Just a displacement?
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// Emit special case [disp32] encoding
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EmitByte(ModRMByte(0, RegOpcodeField, 5), OS);
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, true, OS);
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} else {
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unsigned BaseRegNo = GetX86RegNum(Base);
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if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), OS);
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} else if (!DispForReloc && isDisp8(DispVal)) {
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// Emit the disp8 encoding... [REG+disp8]
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EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), OS);
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EmitConstant(DispVal, 1, OS);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), OS);
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel, OS);
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}
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}
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return;
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}
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// We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP &&
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IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispForReloc) {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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ForceDisp32 = true;
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} else if (DispVal == 0 && BaseReg != X86::EBP) {
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// Emit no displacement ModR/M byte
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EmitByte(ModRMByte(0, RegOpcodeField, 4), OS);
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding.
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EmitByte(ModRMByte(1, RegOpcodeField, 4), OS);
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding.
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EmitByte(ModRMByte(2, RegOpcodeField, 4), OS);
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImm()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base, see Intel
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// Manual 2A, table 2-7. The displacement has already been output.
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = GetX86RegNum(IndexReg);
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else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
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IndexRegNo = 4;
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EmitSIBByte(SS, IndexRegNo, 5, OS);
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} else {
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = GetX86RegNum(IndexReg);
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), OS);
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}
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// Do we need to output a displacement?
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if (ForceDisp8)
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EmitConstant(DispVal, 1, OS);
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else if (DispVal != 0 || ForceDisp32)
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EmitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel, OS);
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}
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void X86MCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = TII.get(Opcode);
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unsigned TSFlags = Desc.TSFlags;
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// FIXME: We should emit the prefixes in exactly the same order as GAS does,
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// in order to provide diffability.
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// Emit the lock opcode prefix as needed.
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if (TSFlags & X86II::LOCK)
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EmitByte(0xF0, OS);
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// Emit segment override opcode prefix as needed.
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switch (TSFlags & X86II::SegOvrMask) {
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default: assert(0 && "Invalid segment!");
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case 0: break; // No segment override!
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case X86II::FS:
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EmitByte(0x64, OS);
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break;
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case X86II::GS:
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EmitByte(0x65, OS);
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break;
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}
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// Emit the repeat opcode prefix as needed.
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if ((TSFlags & X86II::Op0Mask) == X86II::REP)
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EmitByte(0xF3, OS);
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// Emit the operand size opcode prefix as needed.
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if (TSFlags & X86II::OpSize)
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EmitByte(0x66, OS);
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// Emit the address size opcode prefix as needed.
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if (TSFlags & X86II::AdSize)
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EmitByte(0x67, OS);
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bool Need0FPrefix = false;
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switch (TSFlags & X86II::Op0Mask) {
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default: assert(0 && "Invalid prefix!");
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case 0: break; // No prefix!
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case X86II::REP: break; // already handled.
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case X86II::TB: // Two-byte opcode prefix
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case X86II::T8: // 0F 38
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case X86II::TA: // 0F 3A
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Need0FPrefix = true;
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break;
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case X86II::TF: // F2 0F 38
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EmitByte(0xF2, OS);
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Need0FPrefix = true;
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break;
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case X86II::XS: // F3 0F
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EmitByte(0xF3, OS);
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Need0FPrefix = true;
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break;
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case X86II::XD: // F2 0F
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EmitByte(0xF2, OS);
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Need0FPrefix = true;
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break;
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case X86II::D8: EmitByte(0xD8, OS); break;
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case X86II::D9: EmitByte(0xD9, OS); break;
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case X86II::DA: EmitByte(0xDA, OS); break;
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case X86II::DB: EmitByte(0xDB, OS); break;
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case X86II::DC: EmitByte(0xDC, OS); break;
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case X86II::DD: EmitByte(0xDD, OS); break;
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case X86II::DE: EmitByte(0xDE, OS); break;
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case X86II::DF: EmitByte(0xDF, OS); break;
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}
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// Handle REX prefix.
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#if 0 // FIXME: Add in, also, can this come before F2 etc to simplify emission?
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if (Is64BitMode) {
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if (unsigned REX = X86InstrInfo::determineREX(MI))
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EmitByte(0x40 | REX, OS);
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}
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#endif
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// 0x0F escape code must be emitted just before the opcode.
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if (Need0FPrefix)
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EmitByte(0x0F, OS);
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// FIXME: Pull this up into previous switch if REX can be moved earlier.
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switch (TSFlags & X86II::Op0Mask) {
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case X86II::TF: // F2 0F 38
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case X86II::T8: // 0F 38
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EmitByte(0x38, OS);
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break;
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case X86II::TA: // 0F 3A
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EmitByte(0x3A, OS);
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break;
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}
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// If this is a two-address instruction, skip one of the register operands.
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unsigned NumOps = Desc.getNumOperands();
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unsigned CurOp = 0;
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if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
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++CurOp;
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else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
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// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
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--NumOps;
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// FIXME: Can we kill off MRMInitReg??
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unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
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switch (TSFlags & X86II::FormMask) {
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default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
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assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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case X86II::RawFrm: {
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EmitByte(BaseOpcode, OS);
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if (CurOp == NumOps)
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break;
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assert(0 && "Unimpl RawFrm expr");
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break;
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}
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case X86II::AddRegFrm: {
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EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)),OS);
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if (CurOp == NumOps)
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break;
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const MCOperand &MO1 = MI.getOperand(CurOp++);
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if (MO1.isImm()) {
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unsigned Size = X86II::getSizeOfImm(TSFlags);
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EmitConstant(MO1.getImm(), Size, OS);
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break;
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}
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assert(0 && "Unimpl AddRegFrm expr");
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break;
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}
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case X86II::MRMDestReg:
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EmitByte(BaseOpcode, OS);
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EmitRegModRMByte(MI.getOperand(CurOp),
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GetX86RegNum(MI.getOperand(CurOp+1)), OS);
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CurOp += 2;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), OS);
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break;
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case X86II::MRMDestMem:
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EmitByte(BaseOpcode, OS);
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EmitMemModRMByte(MI, CurOp,
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GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
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0, OS);
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CurOp += X86AddrNumOperands + 1;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), OS);
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break;
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case X86II::MRMSrcReg:
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EmitByte(BaseOpcode, OS);
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EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
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OS);
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CurOp += 2;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), OS);
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break;
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case X86II::MRMSrcMem: {
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EmitByte(BaseOpcode, OS);
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// FIXME: Maybe lea should have its own form? This is a horrible hack.
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int AddrOperands;
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if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
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Opcode == X86::LEA16r || Opcode == X86::LEA32r)
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AddrOperands = X86AddrNumOperands - 1; // No segment register
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else
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AddrOperands = X86AddrNumOperands;
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// FIXME: What is this actually doing?
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intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
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X86II::getSizeOfImm(TSFlags) : 0;
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EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
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PCAdj, OS);
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CurOp += AddrOperands + 1;
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if (CurOp != NumOps)
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EmitConstant(MI.getOperand(CurOp++).getImm(),
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X86II::getSizeOfImm(TSFlags), OS);
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break;
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}
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}
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#ifndef NDEBUG
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if (!Desc.isVariadic() && CurOp != NumOps) {
|
|
errs() << "Cannot encode all operands of: ";
|
|
MI.dump();
|
|
errs() << '\n';
|
|
abort();
|
|
}
|
|
#endif
|
|
}
|