llvm-6502/test/CodeGen/AArch64/neon-load-store-v1i32.ll
2014-04-18 13:16:55 +00:00

31 lines
1.0 KiB
LLVM

; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
; arm64 does not use these pseudo-vectors, and they're not blessed by the PCS. Skipping.
; Test load/store of v1i8, v1i16, v1i32 types can be selected correctly
define void @load.store.v1i8(<1 x i8>* %ptr, <1 x i8>* %ptr2) {
; CHECK-LABEL: load.store.v1i8:
; CHECK: ldr b{{[0-9]+}}, [x{{[0-9]+|sp}}]
; CHECK: str b{{[0-9]+}}, [x{{[0-9]+|sp}}]
%a = load <1 x i8>* %ptr
store <1 x i8> %a, <1 x i8>* %ptr2
ret void
}
define void @load.store.v1i16(<1 x i16>* %ptr, <1 x i16>* %ptr2) {
; CHECK-LABEL: load.store.v1i16:
; CHECK: ldr h{{[0-9]+}}, [x{{[0-9]+|sp}}]
; CHECK: str h{{[0-9]+}}, [x{{[0-9]+|sp}}]
%a = load <1 x i16>* %ptr
store <1 x i16> %a, <1 x i16>* %ptr2
ret void
}
define void @load.store.v1i32(<1 x i32>* %ptr, <1 x i32>* %ptr2) {
; CHECK-LABEL: load.store.v1i32:
; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+|sp}}]
; CHECK: str s{{[0-9]+}}, [x{{[0-9]+|sp}}]
%a = load <1 x i32>* %ptr
store <1 x i32> %a, <1 x i32>* %ptr2
ret void
}