Bruno Cardoso Lopes 4e694c96f1 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, ... nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132323 91177308-0d34-0410-b5e6-96231b3b80d8		2011-05-31 02:54:07 +00:00
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Alpha
ARM	On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.	2011-05-29 19:50:32 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic
MBlaze
Mips	This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,	2011-05-31 02:54:07 +00:00
MSP430
PowerPC
PTX
SPARC
SystemZ
Thumb
Thumb2
X86	Use the dwarf->llvm mapping to print register names in the cfi	2011-05-30 20:20:15 +00:00
XCore